Lecture 6 Lecture 6 Logic Simulation Logic Simulation

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What is simulation? Design verification Circuit modeling True-value simulation algorithms

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Compiled-code simulation Event-driven simulation

Summary

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VLSI Test: Bushnell-Agrawal/Lecture 6

Definition: Simulation refers to modeling of a design, its function and performance. A software simulator is a computer program; an emulator is a hardware simulator. Simulation is used for design verification:
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Simulation Defined Simulation Defined

Validate assumptions Verify logic Verify performance (timing) Logic or switch level Timing Circuit Fault
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Types of simulation:
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Simulation for Simulation for Verification Verification

Specification

Synthesis
Response Design Design analysis changes (netlist)

Computed responses

True-value simulation

Input stimuli

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Modules, blocks or components described by

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Modeling for Modeling for Simulation Simulation

Input/output (I/O) function Delays associated with I/O signals Examples: binary adder, Boolean gates, FET, resistors and capacitors ideal signal carriers, or ideal electrical conductors

Interconnects represent
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Netlist: a format (or language) that describes a design as an interconnection of modules. Netlist may use hierarchy.
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a b

Example: A FullExample: A FullAdder Adder c

e d

HA

HA; inputs: a, b; outputs: c, f; AND: A1, (a, b), (c); AND: A2, (d, e), (f); OR: O1, (a, b), (d); NOT: N1, (c), (e);

A B C

HA1

D E

HA2

FA; Carry inputs: A, B, C; outputs: Carry, Sum; Sum HA: HA1, (A, B), (D, E); HA: HA2, (E, C), (F, Sum); OR: O2, (D, F), (Carry);

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VLSI Test: Bushnell-Agrawal/Lecture 6

pMOS FETs V DD

Logic Model of MOS Logic Model of MOS Circuit Circuit

a c b Da Db Dc c

a b

Ca Cb

Cc

nMOS FETs

D a and D b are interconnect or propagation delays

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C a , C b and C c are parasitic capacitances

D c is inertial delay VLSI Test: Bushnell-Agrawal/Lecture 6 of gate

Options for Inertial Options for Inertial Delay Delay

Inputs
a b c (CMOS) c (zero delay)

(simulation of a NAND gate) Transient (simulation of a NAND gate)

region

Logic simulation

c (unit delay)
X Unknown (X) rise=5, fall=5 min =2, max =5

c (multiple delay) c (minmax delay)

0
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Time units
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Two-states (0, 1) can be used for purely combinational logic with zero-delay. Three-states (0, 1, X) are essential for timing hazards and for sequential logic initialization. Four-states (0, 1, X, Z) are essential for MOS devices. See example below. Analog signals are used for exact timing of digital logic and for analog circuits.
Z (hold previous value)

Signal States Signal States

0
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0
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Modeling Levels Modeling Levels

Modeling level Circuit description Signal values 0, 1 0, 1, X and Z Timing Clock boundary Zero-delay unit-delay, multipledelay Zero-delay Application Programming Function, language-like HDL behavior, RTL Logic Connectivity of Boolean gates, flip-flops and transistors Transistor size and connectivity, node capacitances

Architectural and functional verification Logic verification and test Logic verification Timing verification

Switch

0, 1 and X

Timing Circuit

Transistor technologyAnalog voltage data, connectivity, node capacitances Tech. Data, active/ passive component connectivity

Fine-grain timing

Digital timing Analog Continuous and analog voltage, time circuit current verification
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Compiled-code simulation
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True-Value Simulation True-Value Simulation Algorithms Algorithms

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Applicable to zero-delay combinational logic Also used for cycle-accurate synchronous sequential circuits for logic verification Efficient for highly active circuits, but inefficient for low-activity circuits High-level (e.g., C language) models can be used Only gates or modules with input events are evaluated (event means a signal change) Delays can be accurately simulated for timing verification Efficient for low-activity circuits Can be extended for fault simulation
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Event-driven simulation
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Compiled-Code Compiled-Code Algorithm Algorithm

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Step 1: Levelize combinational logic and encode in a compilable programming language Step 2: Initialize internal state variables (flipflops) Step 3: For each input vector Set primary input variables Repeat (until steady-state or max. iterations)
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Execute compiled code

Report or save computed variables

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Event-Driven Event-Driven Algorithm Algorithm

(Example) (Example)
2 4

Scheduled Activity events list

a =1 c =1 0

2 2

e =1 g =1
Time stack

t = 0 1 2 3 4 5 6 7 8

c = 0

d, e

d = 0 b =1 g
0 4

d = 1, e = 0

f, g

f =0

g = 0

f = 1

Time, t

g = 1
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Time Wheel (Circular Time Wheel (Circular Stack) Stack)

Current time pointer max t=0 1 2 3 4 5 6 7 Event link-list

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Efficiency of EventEfficiency of Eventdriven Simulator driven Simulator

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Simulates events (value changes) only Speed up over compiled-code can be ten times or more; in large logic circuits about 0.1 to 10% gates become active for an input change

Steady 0 0 to 1 event

Large logic Steady 0 block without (no event) activity

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Summary Summary
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Logic or true-value simulators are essential tools for design verification. Verification vectors and expected responses are generated (often manually) from specifications. A logic simulator can be implemented using either compiled-code or event-driven method. Per vector complexity of a logic simulator is approximately linear in circuit size. Modeling level determines the evaluation procedures used in the simulator.
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