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1. Overview of 8051 Architecture, Timing, On-chip Resources, Instruction Set etc. Derivative products 2. Programming the 8051: Basic techniques, tips & tricks. 3. Development Support: Development Boards, Emulators, EPROM Programmers, Compilers, etc. 4. I2C, a simple Multi-master 2-wire serial bus. 5. ACCESS.Bus, an I2C-based protocol for connecting peripherals to workstations/PCs.
The 8051
An 8-bit Microcontroller optimized for control applications.
A Microcontroller because you can make a one-chip system with the one chip containing: Program & Data Memory I/O Ports Serial Communication Counters/Timers Interrupt Control logic A-to-D and D-to-A convertors & so on ...
XTAL2
P O R T 0
EA PS EN ALE P O R T 1
SECONDARY FUNCTIONS
P O R T 3
P O R T 2
ADDRES S BUS
Interrupt Control
4k byte ROM
Timer 1 Timer 0
Counter Inputs
CPU
OSC
Bus Control
I/O Ports
Serial Port
TXD RXD
P0 P2
(Address/Data)
P1
P3
Addressing Space
- 64K X 8 ROM - Program memory. - 64K x 8 RAM - External data memory. - 256 x 8 RAM - Internal data memory. - 128 x 8 Special function registers (SFRs).
Program Memory
- 16 bit Program Counter (PC).
- 16 bit Data Pointer (DPTR).
BIT ADDRESSABLE
REGISTER BANK 2
REGISTER BANK 1
07 R7
R6 R5 R4 R3 REGISTER BANK 0
R2 R1
00 R0
10
11
12
8051 Timing
State 1 State 2 State 3 State 4 State 5 State 6 State 1 State 2
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 XTAL2
P0
P2
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LATCH
A7 - A0 D7 - D0
PSEN
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ADDRESS LATCH
WR RD
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Reset
RST pin is Schmitt trigger input.
External reset is asychronous to the internal clock. RST pin must be high for at least two machine cycles while the oscillator is running. Internal RAM not affected by reset, but indeterminate on power up. Port pins in random state until oscillator starts and algorithm write 1's to them. Reset sets PC to 0000. Typical circuits:
+5V
+5V
8051
10uF RST 8.2K 2.2uF
80C51
RST
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17
F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 IP P3 IE P2 SCON P1 TCON P0 TMOD TL0 SP DPH TL1 DPL TH0 TH1 PCON SBUF PSW ACC B
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19
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F0
RS1
: Carry Flag.
RS0
OV
----
- AC : Auxiliary Carry Flag. - F0 : Flag 0 (available for user). - RS1 : Register Select 1. - RS0 : Register Select 0. - OV : Arithmetic Overflow Flag. -P : Accumulator Parity Flag.
RS1
0 0 1
RSO
0 1 0
Register Bank
0 1 2
Address
00h - 07h 08h - 0Fh 10h - 17h
18h - 1Fh
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I/O Ports
- Four 8-bit I/O ports. - Most have alternate functions. - Quasi-bidirectional: Soft pull-up when port latch contains a 1. Can be used as inputs (30Kohm average pullup). Strong pull-up for 2 CPU cycles during 0 to 1 transitions.
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Port Configuration
CMOS
2 OSC. PERIODS V C C VC C VC C
P1
P2
P3 PORT PIN
NMOS
2 OSC. PERIODS
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Port 0
- As an I/O port:
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Port 1
As an I/O port:
Standard quasi-bidirectional.
- Alternate functions:
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Port 2
- As an I/O port: Standard quasi-bidirectional.
- Alternate functions: High byte of address bus for external program and data memory accesses.
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Port 3
- As an I/O port: Standard quasi-bidirectional.
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Counter / Timers
- Two 16-bit Counter/Timers:
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Timer Modes
- Timer Mode 0 : Emulates 8048 counter/timer (13-bits). 8-bit counter (TL0 or TL1). 5-bit prescaler (TH0 or TH1). - Timer Mode 1 : Simple 16-bit counter. - Timer Mode 2 : 8-bit auto-reload.
Counter in TL0 or TL1. Reload value in TH0 or TH1. Provides a periodic flag or interrupt.
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TF1
Cont r ol
Gat e
I NT1 (Pi n)
The Gate input controls whether the Counter runs while gated by the interrupt signal or not.
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- GATE : Permits INTx pin to enable/disable counter. - C/T : Set for counter operation, reset for timer operation. - M1, M0 :
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- IE1, IE0 : Edge flag for external interrupts 1 and 0. * Set by interrupt edge, cleared when interrupt is processed. - IT1, IT0 : Type bit for external interrupts. * Set for falling edge interrupts, reset for 0 level interrupts. * = not related to counter/timer operation.
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Serial Interface
- Full duplex UART. - Four modes of operation: Synchronous serial I/O expansion. Asynchronous serial I/O with variable baud rate. Nine bit mode with variable baud rate. Nine bit mode with fixed baud rate. - 10 or 11 bit frames. - Interrupt driven or polled operation. - Registers: SCON - Serial port control register. SBUF - Read received data. - Write data to be transmitted. PCON - SMOD bit.
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Multi-Drop Communication
Serial Communication Modes 2 and 3 allow one "Master" 8051 to control several "Slaves": The serial port can be programmed to generate an interrupt if the 9th data bit = 1. The TXD outputs of the slaves are tied together and to the RXD input of the master. The RXD inputs of the slaves are tied together and to the TXD ouput of the master. Each slave is assigned an address. Address bytes transmitted by the master have the 9th bit = 1. When the master transmits an address byte, all the slaves are interrupted. The slaves then check to see if they are being addressed or not. The Addressed slave can then carry out the master's commands.
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- SM0, SM1 = Serial Mode: 00 = Mode 0 : Shift register I/O expansion. 01 = Mode 1 : 8-bit UART with variable baud rate. 10 = Mode 2 : 9-bit UART with fixed baud rate. 11 = Mode 3 : 9-bit UART with variable baud rate. - SM2 : Mode 0 : Not used. Mode 1 : 1 = Ignore bytes with no stop bit. Mode 2,3 : 0 = Set receive interrupt (RI) on all bytes. : 1 = Set RI on bytes where bit 9 = 1. - REN = Enables receiver. - TB8 = Ninth bit transmitted (in modes 2 and 3). - RB8 = Ninth bit received: Mode 0 : Not used. Mode 1 : Stop bit. Mode 2,3 : Ninth data bit. - TI = Transmit interrupt flag. - RI = Receive interrupt flag. PHILIPS SEMICONDUCTORS - SIGNETICS. MICROCONTROLLER TRAINING FOILS
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Interrupt System
- 5 Interrupt Sources (in order of priority): External Interrupt 0. Timer 0. External Interrupt 1. Timer 1. Serial Port. - Each interrupt type has a separate vector address. - Each interrupt type can be programmed to one of two priority levels. - External interrupts can be programmed for edge or level sensitivity.
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: Global interrupt enable. : Serial interface. : Timer 1. : External interrupt 1. : Timer 0. : External interrupt 0. - 0 = Disabled. - 1 = Enabled.
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- PS - PT1
- PX1
- PT0 - PX0
: External interrupt 1.
: Timer 0. : External interrupt 0.
0 = Low priority.
1 = High priority.
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Controlled Power Reduction Idle State Power down state Power savings in CMOS ports General purpose software flags
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SMOD
----
----
----
GF1 GF0
PD
IDL
- POWER DOWN OPERATION Setting PD bit stops oscillator. RAM contents are saved. Exit via Reset. Some (newer) 80C51 derivatives allow Power-Down wakeup via Interrupt.
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Serial interface. External interrupts. Timers. Exit with any enabled interrupt or Reset. - GF0, GF1 are general purpose software flags. - SMOD serial interface control bit. Doubles baud rate in modes 1,2, and 3. - Only SMOD available on NMOS parts.
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Power Consumption
Example : for 80C51 at Vcc = 5V. Mode / Freq. 0.5 MHz 16 MHz
Operating
Idle Power Down
2.2 mA
0.9 mA 50 uA
20.5 mA
5.0 mA 50 uA
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Operands
A, Rn A, direct A, @Ri A, #data
Bytes/Cycles
1/1 2/1 1/1 2/1 1/1 1/1 2/1 1/1 1/2 1/4 1/4 1/1
INC DEC
A Rn direct @Ri
DPTR AB AB A
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Operands
A, Rn A, direct A, @Ri A, #data direct, A direct, #data C, bit C, /bit
Bytes/Cycles
1/1 2/1 1/1 2/1 2/1 3/2 2/2 2/2 1/1 1/1 2/1
CLR CPL
A C bit
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49
50
51
(cont'd)
Bytes/Cycles 1/2
A, @A+PC
PUSH POP direct direct
1/2
2/2 2/2
XCH
A, Rn
A, direct A, @Ri
1/1
2/1 1/1 1/1
XCHD
A, @Ri
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ACALL
RET RETI LJMP AJMP SJMP JMP JZ JNZ
addr11
addr16 addr11 rel @A+DPTR rel rel
2/2
1/2 1/2 3/2 2/2 2/2 1/2 2/2 2/2
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(cont'd)
Bytes/Cycles 3/2
A, #data, rel
Rn, #data, rel @Ri,#data,rel DJNZ Rn, rel direct, rel NOP JC JNC JB JNB JBC rel rel bit, rel bit, rel bit, rel
3/2
3/2 3/2 2/2 3/2 1/1 2/2 2/2 3/2 3/2 3/2
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The I2 C BUS
(Inter - Integrated Circuit)
A 2 wire serial data and control bus Implemented with one serial data (SDA) and one clock (SCL) line. Unique start and stop conditions. Slave selection protocol uses a 7-Bit slave address. Bi-directional data transfer. Acknowledgement after each byte transferred. No limit on the number of bytes transferred. Real multimaster capability.
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I2C Definitions
MASTER:
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SCLK1 OUT
DATA1 OUT
SCLK2 OUT
DATA2 OUT
SCLK IN
DATA IN
SCLK IN
DATA IN
DEVICE 2
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Both start and stop conditions are generated by bus master. The Bus is busy after a start condition.
SDA
SCL
S Start Condition
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SDA SCL
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I2C Address
Each node has a unique 7 bit address. Peripherals usually have fixed and programmable address portions. Addresses starting with 0000 or 1111 have special functions. 0000000 is a general call address.0 a null address. reserved for future bus expansion 0000001 is 1111xxxx is
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MSB
LSB
ACK
R/W
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Acknowledgement
Master/slave receivers pull data line low for one clock pulse after reception of a byte. Master receiver leaves data line high after receipt of the last byte requested. Slave receiver leaves data line high on the byte following the last byte it can accept.
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SDA MSB SCL S START CONDITION 1 2 7 8 9 ACK 1 2 3-8 9 ACK P STOP CONDITION
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Master Read:
S SLAVE ADDRESS R A DATA A DATA NA P
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It can also be used as a handshake by a slave device to slow data transfer from a master.
The clock synchronization procedure consists of two algorithms: 1) If the clockline goes low when a master is asserting a high, the master asserts a low and starts to time out its low clock period. 2) When a master stops asserting a low on the clock line, it waits until the clockline actually goes high before starting to time the high period.
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SCL
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Multimaster situations require two additional features of the I2C protocol. ARBITRATION: Arbitration is the procedure by which competing masters decide final control of the bus.
I2C arbitration does not corrupt the data transmitted by the prevailing master.
Arbitration is performed bit by bit until it is uniquely resolved. Arbitration is lost by a master when it attempts to assert a high on the data line and fails..
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DATA1
DATA2
SDA
SCL
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Microcontrollers Microprocessors General Purpose Peripherals I/O, Memory, Display, DAC, ADC, Clock/Calendar Peripherals for Specific Target Martkets Audio, Telephony, Video
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ACCESS.bus .1
DEC has invented an interconnect method for connecting a PC or Workstation to low speed I/O devices such as: Keyboards
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ACCESS.bus .2
ACCESS.bus features: 80 KBps Peak Bandwidth Hot plugging and unplugging of devices (keyboard, mouse, etc.) Up to 14 devices Up to 8 Meters (26.4 feet) in length Serial, daisy-chained 4-pin cable (2 pins are power and ground). Only ONE device port needed on computer.
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ACCESS Bus .3
ACCESS.Bus features: Layered 3-layer protocol defined by DEC: Physical layer is I2C. Base Protocol over I2C defines the structure of I2C messages and defines Control and Status Messages. Also supports auto-addressing and hot plugging.
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ACCESS.Bus .4
Device address and type recognition is automatic. No drivers have to be loaded. Concise protocol. Only 7 standard message types. Fully implemented in the 87C751 with 2K of Program memory. ACCESS.Bus is part of DEC's ARC and ACE platforms. Fully open and free. No royalties. DEC and Signetics will provide Developer's Kit with all information required to to develop applications. DEC's TRI/ADD developer program will provide technical support, documentation and updates, technical seminars, and newsletters and assist with marketing support.
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ACCESS.bus .5
The closest thing to the ACCESS.bus is Apple's ADB (Apple Desktop Bus). The following is a comparison between ADB and ACCESS.bus: ADB not recommended 10 KBits/sec 3 devices Proprietary 5 meters ACCESS.bus fully supported 80 KBits/sec 14 devices Open. No royalties 8 meters
Hot-Plugging Peak data rate Daisy-chain limit 3rd party access Max. cable length
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Extended I/O
80C51
Memory 2 to 32 K
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CEPROM 4K CEPROM 4K CEPROM 8K CEPROM 8K CEPROM 8K CEPROM 8K CEPROM 16K CEPROM 16K CEPROM 32K
UART, I2C 3
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80C51 Coding:
Ideas and Examples
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RTEX:
RET
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Compare
The 80C51 has no basic compare instruction. However, the CJNE (compare and jump if not equal) instruction leaves the carry flag set after execution, allowing further magnitude comparisons to be made. This method works for all variations of CJNE: CJNE A,direct,rel
CJNE
CJNE CJNE
A,#data,rel
Rn,#data,rel @Ri,#data,rel
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Compare
Examples of four variations of magnitude comparison: CJNE Test: JC CJNE Test: JNC CJNE SJMP Test: Else: JNC ----CJNE SJMP Test: JNC A,Value,Test LTE LTE ;Branch if A <= Value. A,Value,Test LT A,Value,Test GTE A,Value,Test Else GT ;Branch if A > Value. ;Branch if A >= Value. ;Branch if A < Value.
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Read-Modify-Write
Most instructions that reference 80C51 port data read the value on the port pins rather than the value in the port latch. However, some instructions read the port latch instead.
1) Arithmetic or logical operations that may alter port values: ANL port,src ORL port,src XRL port,src INC port DEC port DJNZ port,label 3) Instructions that may alter port bits: MOV bit,C JBC bit,label CPL bit CLR bit SETB bit
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The 80C51 does not have any specific built-in facility for allowing a hardware single step operation. However, when a Return from Interrupt instruction is executed, at least one instruction from the originally interrupted routine is always executed before another interrupt may be serviced. Thus, if execution of RETIs are carefully controlled while an interrupt is pending, a software single step may be effected.
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ExInt0:
86
start timer
stop timer
Assumption: use external interrupt 0 for the pulse input. Use timer 0 in gated mode.
Note: to measure pulse low time in this manner, the input must be inverted externally.
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;External interrupt 0 service routine. ExInt0: CLR TR0 MOV ValH,TH0 MOV ValL,TL0 MOV TH0,#0 MOV TL0,#0 SETB TR0 RETI
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start timer
stop timer
Note: this method may entail some loss of precision due to the possibility of variable interrupt latency.
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;External interrupt 0 service routine. ExInt0: CPL JB MOV MOV MOV MOV INT0EX: RETI TR0 TR0,INT0EX ValH,TH0 ValL,TL0 TH0,#0 TL0,#0 ;Clear timer so another sample can ; be taken. ;Complement the timer run flag. This starts ; and stops the timer on alternate interrupts. ;Exit if timer is running. ;Otherwise sample the timer value.
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stop pulse
Note: the precision of pulses generated using this method will vary depending on the interrupt latency of the timer interrupt.
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;Tiimer 0 interrupt routine. T0INT: CLR CLR RETI P2.0 TR0 ;End of pulse (use SETB for a low going pulse). ;Stop timer.
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repeat
Note: the precision of pulses generated using this method will vary depending on the interrupt latency of the timer interrupt.
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Note: for higher frequency pulses, it may be possible to use the timer reload feature (mode 2) to obtain more accurate pulse durations.
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{ {
0000
95
;Read in a source block byte. ;Write byte out to destination block. ;Increment 'to' memory pointer. ;Increment 'from' memory pointer.
L1:
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97
Start Transmit
Exit
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Exit
99
Receive?
100
Done? N
Exit
101
First bit? Y
Done? N
Look for STOP (set error flag and abort if not found).
Look for START (set error flag and abort if not found).
Exit
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Supported Microcontrollers
Type 1 (full support via RS-232 to PC) 8031/51 8032/52 8xC31/51 8xC32/52 8xC451 8xC550 8xC552 8xC528 8xC652/654 8xC851
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The 8xC751 and 8xC752 have no external program memory capability and do not support user program loading on the DB-51. The 8xC410 does not have an on-chip UART and must be communicated with via its I2C port. The current version of the DB-51 does not support user program loading on the 8xC410.
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MS -DOS Compatible PC
RS -232 Interface
Type 1 Microcontroller
I2C bus
Type 2 Microcontroller
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Emulators
Nohau Corp. BSO/Tasking
51 E. Campbell Ave.
Campbell, CA 95008 (408) 866-1820 MetaLink Corp.
Signum Systems
171 E. Thousand Oaks Blvd., #202 Thousand Oaks, CA 91360 (805) 371-4608
And others...
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Metalink macro cross assembler ASM51 Public Domain! Free on the Signetics BBS 2500 AD software Macro assembler Cross assembler Simulator / debugger And a host of others...
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8051 C Compilers
Archimedes Software, Inc. 2159 Union Street San Francisco, CA 94123-9923 (415) 567-4010 Avocet Systems, Inc. 120 Union Street P.O. Box 490 BP Rockport, Maine 04856 (800) 448-8500 BSO/Tasking 128 Technology Center PO Box 9164 Waltham, MA 02254-9164 (617) 894-7800 Franklin Software, Inc. 888 Saratoga Ave., #2 San Jose, CA 95129 (408) 296-8051 And others... 2500 AD Software, Inc. 109 Brookdale Avenue P.O. Box 480 Buena Vista, CO 81211 (800) 843-8144
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