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Topics
Architectural issues. Switch logic, Gate Logic. Examples of Structured Design - Combinational logic - Design of an ALU subsystem Consideration of Adders, Multipliers. Sequential Circuits. Semiconductor Memories.
Introduction
Large systems are composed of sub-systems, known as Leaf-Cells The most basic leaf cell is the common logic gate (inverter, nand, ..etc) Structured Design
High regularity Leaf cells replicated many times and interconnected to form the system
Divide and conquer - limit the number of components you deal with at any one time Group several components into larger components
transistors form gates gates form functional units functional units form processing elements
A System-on-a-Chip
Courtesy: Philips
Specification Description of requirements Systems Level placing and interconnecting major functional units Function Level specification and design of major functional units Logic/Circuit Level Gate level design, gate interconnection design Layout Level what will actually be patterned onto the chip, how the chip will be processed Physics Level the physics of gate and switch operation
Define the requirements. Partition the overall architecture into subsystems. Consider interconnection paths between the subsystems. System floor plan on silicon chip. Regular structures for replication. Stick diagram for each leaf-cell (module) in the system. Convert the stick diagram of each leaf-cell into layout and go for design rule check. Simulate the performance of each cell.
Design Validation
Must check at every step that errors have not been introduced
the longer the error remains the more expensive it becomes to remove it
After high level design is complete, it is necessary to decide on how design is to be implemented in silicon The implementation plan is known as the floor plan First step in laying out a floor plan is the routing of supply and clock rails In doing this sufficient space must be left between power rails to allow for data-buses and combinational logic cells Decide on relative positions of major functional blocks Use routing algorithm ( software ) Routing algorithm will minimize total routing area.
Switch Logic
How do we build switches from MOS transistors? 1) Pass Transistors 2) Transmission gates
Pass Transistors
Require one transistor and one gate signal Transmit 0 well, but when Vdd is applied to the drain, the voltage at the source is Vdd-Vtn When switch logic drives gate logic, n-type switches can cause electrical problems
When n-type switch driving a complementary gate cause the gate to run slower when the switch input = 1
Since pull down current is weaker when a lower gate voltage is applied The complementary gates pull down will not suck current off the output capacitance as fast as it should be
When Vin= Vdd , then Vout= Vdd When Vin=0, CL will be discharged through P-transistor until Vout= Vtp P-device will stop conducting Logic 0 is somewhat degraded through p-device.
V s = |V tp | V SS
V DD V DD
V DD -V tn V DD -2V tn
(a)
A A B B Inverse Pass-Transistor Network F
(b)
Advantages:
Disadvantages:
Output voltage degrades. Not an ideal switch due to series resistance. Delay of series pass transistors is large.
Transmission gates
Advantages:
Less no. of Transistors compared to CMOS. No Static Power Consumption. Efficient building of complex gates.
Disadvantages:
Not an ideal switch due to series resistance. Delay of series transmission gates is large.
Gate Logic
The following parameters are calculated for different sizes of nmos inverter.
Zp.u / Zp.d ratio Pull-up and Pull-down resistance. Power dissipation. Standard unit of capacitance Gate delay.
The ratio between p.u to all p.d transistors (Zp.u / nZp.d) must be minimum 4:1 for making correct level of output voltage.
Since the pull down transistors are parallel in Nor gate, i.e. the pull down ratio for all transistors is same. So, it has same characteristics as inverter. The area occupied is reasonable, since there is no increase in length of pull-up transistor. So, Nor gate is preferable than nand gate.
CMOS Logic
CMOS Nand Gate has no restrictions as NMOS Nand Gate, but we have to keep the geometry symmetry by Allowing extended fall times for series nmos transistors (for series resistance). Keep the transfer characteristics for Vdd/2. CMOS Nor Gate has series p-transistors which increase the resistance and delay. This effect the transfer characteristics and reduce noise immunity. So, Geometries of nmos and pmos transistors should change.
CMOS Logic
Static CMOS Logic Pseudo NMOS Logic Dynamic CMOS Logic Domino CMOS Logic Clocked CMOS Logic n-p CMOS Logic
A
Rp Rp B Rn B Rn A Cint A CL Rn A CL Rn A Rn B CL A INV Rp B Rp Cint Rp
Rp A Rn B Rn A B
Rp
CL
Cint
Delay (psec) 67 64 61 45
Voltage [V]
A=1, B=10
200 300 400
80 81
A= 10, B=1
time [ps]
PUN F PDN
Static CMOS
The pulldown network of the gate is the same as for a fully complementary gate. The pullup network is replaced by a single p-type transistor whose gate is connected to VSS leaving the transistor permanently on. The p-type transistor is used as a resistor. When the gate input is 0V, both n-type transistors are off and the p-type transistor pulls the gates output up to VDD. When the gate input is Vdd, both the p-type and n-type transistor are on and both are operating to determine the gates output voltage.
2.0
W/Lp = 4
Vou t [V]
1.5
W/Lp = 2
1.0
0.5
W/Lp = 1
0.0 0.0
0.5
1.0
1.5
2.0
2.5
Vin [V]
Main advantage of the pseudo-nMOS gate is the small size of the pullup network, both in terms of number of devices and wiring complexity. Disadvantages: Due to more pull-up resistance, delay is more and hence speed of circuits is less. More Static power dissipation due to conduction path between VDD and VSS
The disadvantage of Static Power dissipation in Pseudo NMOS Logic leads for an alternative logic which is Dynamic CMOS Logic. It avoids Static Power dissipation and adds a clock input for precharge and conditional evaluation phases.
Mp
Out CL
PDN
Me
In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.
Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.
Precharge. When CLK goes low, the p-type transistor starts charging the precharge capacitance. The pulldown transistors controlled by the clock keep that precharge node from being drained. The length of CLK = 0 phase is adjusted to ensure that the storage node is charged to a solid logic 1. Evaluate. When CLK goes high, precharging stops i.e. the p-type pullup turns off. The evaluation phase begins i.e. the n-type pulldown turns on. The input signals must monotonically riseif an input goes from 0 to 1 and back to 0, it will inadvertently discharge the precharge capacitance. If the inputs create a conducting path through the pulldown network, the precharge capacitance is discharged, forcing its gates output to 0. If input is not 1, then the gates output would be left charged at logic 1.
Conditions on Output
Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL
Clk
off Mp on
1 Out ((AB)+C) C
A B Clk off Me on
Logic function is implemented by the PDN only Full swing outputs (VOL = GND and VOH = VDD) Non-ratioed sizing of the devices does not affect the logic levels. Faster switching speeds due to reduced load capacitance. Overall power dissipation usually higher than static CMOS. no glitching higher transition probabilities extra load on Clk PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn low noise margin (NML)
Advantages: low area higher speed than static complementary gates. Disadvantages: Precharged gates introduce functional complexity because they must be operated in two distinct phases, Requires introduction of a clock signal. They are also more sensitive to noise; Their clocking signals also consume power and are difficult to turn off to save power.
Clk Out1
Mp
Clk Out2 In
In
Clk
Me
Clk
Me
Out1
VTn V t
Out2
Out2 should remain at VDD since Out1 transitions to 0 during evaluation. However, since there is a finite propagation delay for the input to discharge Out1 to GND, the second output also starts to discharge. The second dynamic inverter turns off (PDN) when Out1 reaches VTn. Correct operation is guaranteed (ignoring charge redistribution and leakage) as long as the inputs can only make a single 0 -> 1 transition during the evaluation period. Setting all inputs of the second gate to 0 during precharge will fix it.
Out1
PDN
Me
Precharge Phase (Same as Dynamic Logic) Evaluate Phase (Modification to Dynamic Logic).
When CLK goes high, precharging stops i.e. the p-type pullup turns off. The evaluation phase begins i.e. the n-type pulldown turns on. The input signals must monotonically riseif an input goes from 0 to 1 and back to 0, it will inadvertently discharge the precharge capacitance. If the inputs create a conducting path through the pulldown network, the precharge capacitance is discharged, forcing its value to 0 and the gates output (through the inverter) to 1. If input is not 1, then the storage node would be left charged at logic 1 and the gates output would be 0.
Only non-inverting logic can be implemented. Smaller area compared to Static CMOS. Free of glitches due to transistion from logic 1 to logic 0 only. Very high speed
static inverter can be skewed, only L-H transition Input capacitance reduced smaller logical effort
Out1
Clk
00 01
Mp
Out2
PDN
PDN
Me
Me
Ensures all inputs to the Domino gate are set to 0 at the end of the precharge period. Hence, the only possible transition during evaluation is 0 -> 1
It is a combination of
Static CMOS Clk input given to one additional NMOS. Clk input given to another additional PMOS.
Fan-in for this logic is 2n+2. When Clk goes high, then logic of the circuit is evaluated due to NMOS in ON condition. When Clk goes low, then Logic is not evaluated due to NMOS in OFF condition.
An elegant solution to the dynamic CMOS logic erroneous evaluation problem is to use NP Domino Logic (also called NORA logic) as shown below.
N logic stages use true clock, normal precharge and evaluation phases, with N logic tree in the pull down leg. P logic stages use a complement clock, with P logic stage tied above the output node. During precharge clk is low (-clk is high) and the P-logic output precharges to ground while N-logic outputs precharge to Vdd. During evaluate clk is high (-clk is low) and both type stages go through evaluation; N-logic tree logically evaluates to ground while Plogic tree logically evaluates to Vdd.
Inverter outputs can be used to feed other N-blocks from Nblocks, or to feed other P-blocks from P-blocks
Example
BiCMOS Technology
CMOS properties:
BJT properties:
Basic Circuits
BiCMOS Circuits
Inverter
Nand Gate
Structured Design
5-way selector. Multiplexers & Demultiplexers. Encoders & Decoders. Parity Generator. Bus Arbitration Logic. Gray Code to Binary Code Converter.
Adders
32-bit Adders
Sum Output
Carry output
G=AB
Propagate: Cout = C
P=AB
K = ~A ~ B
The carry input is precharged with clock signal instead of passing through the Logic. Carry path is gated by Propagate signal (P=A^B) with a single n-type pass transistor. Generate signal (G= A.B)
Carry-Ripple Adder
Critical path goes from Cin to Cout Design full adder to have fast carry delay
B4 A3 C3 B3 A2 C2 S3 S2 B2 A1 C1 S1 B1 Cin
A4 Cout S4
To avoid the linear growth of the carry delay, we use a Carry Look-Ahead Adder (CLA) in which the carries can be generated in parallel. Output Carry is represented in terms of generate and propagate signals. The Expressions for 4-bit CLA are
C1=G0+P0C0
It is also referred as Conditional sum adder. The adder is divided into two blocks
One block with logical 0 Cin. Another block with logical 1 Cin.
The Delay of n-bit adder is given by T=P.K1+(M-1).K2 where, M=No. of Blocks in the adder. P=No. of Cells of each block. K1=Delay through one adder cell. K2 = Delay through Multiplexer.
It is also called as Carry Bypass Adder. Looks for cases in carry-out of a set of bits is identical to carry in. Typically organized into m-bit stages. If Ai Bi , for every bit in stage, then bypass gate sends stages carry input directly to carry output.
ci+1
FA
ci+1
FA
ci
si+1
pi+1
si
pi
skip signal
If (P0 and P1 and P2 and P3 = 1) then C3 = C0 else C3=output carry of stage4 adder
Delay of CSA
Worst case delay T is given by, T=2(P-1)K1+(M-2)K2, where k1=delay through one adder cell k2=delay for skipping the carry over a block
Comparison of Adders
MULTIPLIERS
Multipliers: Basics
4-bit Multiplier
Multipliers
Serial parallel Multiplier Braun Array 2s Complement multiplication using Baugh-Wooley method Pipelined Multiplier Array Modified Booths Algorithm Wallace Tree Multipliers Recursive decomposition of Multiplication Daddas Method
Serial-Parallel Multiplier
Braun Array
A Wallace tree is an implementation of an adder tree designed for minimum propagation delay. Completion time is proportional to log2n. Optimized column adder tree Combines all partial products into 2 vectors (carry and sum) . Carry and sum outputs combined using a conventional adder. Compresses the no. of stages of partial products.
Sequential Logic
Complex systems are designed in Top-Down approach with the help of CAD tools. Partition the system sensibly. Aiming for simple interconnection and high regularity between sub-systems. Generate and verify each section of the design. Calculate the dimensions of the layout of subsystems and check the proportion in the total chip area.