Embedded Hardware

Embedded System Hardware

Embedded system hardware is used for processing of input to produce output in task specific fashion

Input Interface

Information Processing System

Output Interface

Processors
Microprocessors and Micro-controllers

Key requirements: Energy-efficiency High Code Density

Microprocessors
CPU for Computers No RAM, ROM, I/O on CPU chip itself Example: Intels x86, Motorolas 680x0
CPU GeneralPurpose Microprocessor

Data Bus

Many chips on mother-board

RAM

ROM

I/O Port

Timer

Serial Port

Address Bus

General-Purpose Microprocessor System

What is Micro-controller?
Basically, a micro-controller is a device which integrates a number of the components of a microprocessor system onto a single microchip. A micro-controller combines onto the same microchip:
The CPU core Memory (both ROM and RAM) Some parallel digital I/O & more

Micro-controller

Source: www.ami.bolton.uk

Components of a Micro-controller
A Timer module to allow the micro-controller to perform tasks for certain time periods. A serial I/O port to allow data to flow between the micro-controller and other devices such as a PC or another microcontroller. An ADC to allow the micro-controller to accept analogue input data for processing.

Micro-controller

Source : An Introduction to the design of small-scale embedded systems , Tim Wilmshurst, palgrave 2001

Why Micro-controller?
Low cost, small packaging Low power consumption Programmable, re-programmable Lots of I/O capabilities Easy integration with circuits For applications in which cost, power and space are critical Single-purpose

Basics of Architecture

VonNeuman Architecture
Only one bus between CPU and memory RAM and program memory share the same bus and the same memory, and so must have the same bit width Bottleneck: Getting instructions interferes with accessing RAM
Program and Data Memory
BUS

Harvard Architecture
Separate program bus and data bus: can be different widths!
Instruction Pipelining easy

Data Memory

Program Memory

8-Bits 12/14/16-Bits

CISC Complex Instruction Set Computer

A large number of instructions each carrying out a different permutation of the same operation Instructions provide for complex operations Different instructions of different format Different instructions of different length Different addressing modes Requires multiple cycles for execution

RISC Reduced Instruction Set Computer

Instructions for simple operations that can be executed in a single cycle Each instruction of fixed length
Facilitates instruction pipelining

Large general purpose register set

Can contain data or address (symmetry)

Load-store Architecture
No memory access for data processing instructions

PIC Micro-controller Family

One of the Leading Architectures for low end applications

PIC Architecture
PICs are RISC Reduced Instruction Set Computer (RISC) Few instructions (usually < 50) Only a few addressing modes Executes 1 instruction in 1 internal clock cycle (Tcyc)

The PIC Family: Packages

PICs come in a huge variety of packages:
Examples: 8 pin : 18pin : 28pin : 40pin : 44 - 68pin : (16bit) 12C50x (12bit) and 12C67x (14bit) 16C5X (12bit), 16Cxxx (14bit) 16C5X (12bit), 16Cxxx (14bit) 16Cxxx (14bit), 17C4x (16bit) 16Cxxx (14bit), 17C4x / 17Cxxx

PIC Mid-range Block Diagram

Ref: PIC architecture reference manual

Peripheral Components

The PIC Family: Speed

PICs require a clock to work. Can use crystals, clock oscillators, or even an RC circuit. Some PICs have a built in 4MHz RC clock Not very accurate, but requires no external components! Instruction speed = 1/4 clock speed (Tcyc = 4 * Tclk)

Clock Frequency
Examples 12C50x 4MHz 12C67x 10MHz 16Cxxx 20MHz 17C4x / 17C7xxx 33MHz 18Cxxx 40MHz

Clocking Scheme

Ref: PIC architecture reference manual

Instruction Execution
Clock internally divided by 4 to generate 4 quadrature clocks Instruction cycle consist of 4 Q cycles PC incremented every Q1 Instruction is fetched from program and latched into instruction register by Q4 Instruction is decoded and executed in the following Q1 to Q4

Instruction Pipelining
Fetch takes one cycle, decode and execute takes another cycle While execution, next instruction can be fetched
No bus conflict due to Harvard Architecture

If instruction changes PC ( e.g. Branch) extra cycle is required to complete instruction

ALU

W: working register

d: destination bit
Ref: PIC architecture reference manual

Status Register
Status register contains
Arithmetic status of ALU operation RESET status Memory bank select bits

TO: time out; PD: power Down; IRP, RP1, RP0: bank select; Z: zero, DC:digit carry (BCD). C: carry

Memory Organization
Program Memory
Data Memory Access to both possible in each cycle because of distinct bus

The PIC Family: Program Memory

EPROM (Erasable Programmable Read Only Memory)
One Time Programmable (OTP) chips are EPROM chips, but with no window! PIC Examples: Any C part: 12C50x, 17C7xx, etc.

Program Memory
FLASH
Re-writable (even by chip itself) Much faster to develop on! Finite number of writes (~100k Writes) PIC Examples: Any F part: 16F84, 16F87x, 18Fxxx (future)

PIC program space is different for each chip.

Program Memory
Mid-range PIC processors have 13 bit Program Counter Width of program memory bus 14 bits Program memory space divided into 4 pages of 2K each

Memory Map
PCLATH (program counter latch high): to jump from one page to another these bits modified
Ref: PIC reference manual

Stack
Mid-range PIC 8-level deep 13 bit wide hardware stack
Not part of program or data memory

PC is pushed onto stack when CALL instruction is executed or Interrupt occurs PCLATH is not modified when PUSHed to or POPed from stack

The PIC Family: Data Memory

PICs use general purpose file registers for RAM (each register is 8 bits for all PICs) Programs are stored in program space (not in data space), so low RAM space. Register File Memory Consist of 2 Components General Purpose Register (GPR) Files Special Purpose Register (SPR) files

Memory organised into banks

16F877 has 4 banks of register

Registers
GPR: Area banked to provide greater than 96 bytes of general purpose RAM SFR: To control the peripheral and core functions like indirect addressing

Summary
We have reviewed architectural features Understood features of processor core of the PIC family of micro-controllers We shall look at instruction set and peripheral components in the next class

PIC: Instruction Set

Simple instruction set : about 35 instructions Instruction set grouped into 3 categories:
Byte-oriented operations Bit-oriented operations Literal and Control operations

Instructions : 14 bit (mid-range) All instructions take one cycle unless conditional test is true or PC is changed as a result of an instruction

Instruction format
Byte-oriented Operation 0..6 : 7 bit file register address 7 : d bit ; 0 for destination W 8..13: opcode Bit-oriented Operation 0..6: 7 bit file register address 7..9: 3-bit bit address within the 8-bit file register 10..13: opcode

Instruction Format
Literal and Control Operations
General
0..7 : 8 bit literal (immediate) value 8..13: opcode

CALL & GOTO instructions

0..10: 11 bit literal value (target address) Upper 2 bits of PC loaded from PCLATH<4:3> 11..13: opcode

Addressing Modes
Direct Addressing

in status register

Ref: PIC reference manual

Indirect Addressing
Full 8-bit register file address is first written into FSR, a special purpose register FSR serves as address pointer to any address through out the entire register file Subsequent direct access of INDF (a SFR) will actually access the register file using the content of FSR as a pointer to the location of operand

Indirect Addressing
in status register

Ref: PIC reference manual

Byte oriented operations Arithmetic and logical operations Data Movement Examples addwf f,d Add contents of W with register f, if d=0 store result in W else store in register f; e.g.: addwf 0x20,0 clrf f Contents of register f are cleared and Z bit (STATUS) is set; e.g.: clrf 0x30 movwf f Move data from W register to register f e.g : movwf 0x04

Instructions

More Byte oriented instructions

decfsz f,d

Decrement register f, place result in f or W depending on value of d; Skip the next instruction if result is zero e.g.: decfsz 0x20,1 Decrement f, place result depending on value of d, effects Z flag e.g : decf 0x30,0

conditional branching

decf f,d

Literal Operations
Immediate addressing mode Examples addlw k Add literal k to register W e.g: addlw 0x05 movlw k Move literal k into register W e.g : movlw 0x21

More on Data transfer Instructions

Move instructions for
A constant being written in W register (MOVLW is short for MOVe Literal to W) For data to be copied from W register onto RAM and data from RAM to be copied onto W register (or on the same RAM location, at which point only the status of Z flag changes).

Instruction CLRF writes constant 0 in 'f ' register, and CLRW writes constant 0 in register W. SWAPF instruction exchanges places of the 4-bit nibbles field inside a register.

More on Arithmetic and Logical Instructions

PIC like many microcontrollers supports only subtraction and addition. Flags C, DC and Z are set depending on a result of addition or subtraction. Since subtraction is performed like addition of a negative value, C flag is inverse following a subtraction. Logic unit of PIC has capability of performing operations AND, OR, EX-OR, complementing (COMF) and rotation (RLF and RRF).

On Rotation instructions
Rotates the register contents through flag C Bits move by one bit to the left (toward bit 7), or to the right (toward bit 0). Bit which "comes out" of a register is written in flag C, and value of C flag is written in a bit on the "opposite side" of the register. Example: rrf f,F(W)
Copy f into F or W, rotate F or W right through the carry bit

Bit Oriented Operations

Manipulate bits in control and status registers Examples bsf f,b Set bit b( where b=0 to 7) in register f e.g. : bsf 0x03, 5 btfsc f,b Test bit b of register f, skip next instruction if bit is 0 e.g. : btfsc 0x03, 2

More on Bit operations

Instructions bcf and bsf perform set or clear one bit anywhere in the memory. Bit operations consist of following microoperations CPU reads the complete byte CPU changes one bit in it Then writes the entire byte back

Control Instructions
Program and Processor Control Examples goto k (k 11 bit) Unconditional branch. Literal k is loaded into PC; e.g. : goto there (use of labels) call k (k 11 bit) Call subroutine at location k; e.g: call sum
Upper 2 bits of PC loaded from PCLATH<4:3>

More Control Instructions

retfie Return from interrupt service routine and re-enable interrupts sleep Go to standby mode

clrwdt
Clear watchdog timer

Directing program flow

GOTO, CALL and RETURN instructions like other micro-controllers Call and return instructions use hardware Stack, independent of internal RAM and limited to eight levels 'RETLW k' instruction is identical with RETURN instruction, except that before coming back from a subprogram a constant defined by instruction operand k is written in W register.

Example Code
Decrement a 16 bit counter:
upper byte of the counter COUNTH & lower byte COUNTL
movf COUNTL,F btfsc STATUS,Z decf COUNTH,F decf COUNTL,F ; Set Z if lower byte =0 ; if so, decrement COUNTH ; decrement COUNTL

Example Code
00h INDF

Example code to clear 0x20 - 7F:

movlw movwf loop clrf incf btfss goto 0x20 FSR INDF FSR,F FSR,7 loop

04h

FSR

7Fh
Register File

Software: Relative Addressing

PCL = Low byte of the Program Counter Can be read and written. Writing to it sets the address of the next instruction to be executed.

14bit core

Using Relative Addressing

Table

Look-up:

movlw 0x04 call Table movwf Result

; Load W with 4 ; Call the table subroutine ; Store the result from the table Table addwf PCL, W ; Jump to(current PCL)+W retlw 0x00 ; Return with 0x00 in W retlw 0x23 ; Return with 0x23 in W retlw 0x33 ; etc. retlw 0x88

Assembly Language Programming

Advantage of using symbolic address and data references MPASM assembler for PIC family of processors
Uses specification of the target processor provided in .INC file Assembler directives for specifying configuration details ( bits in device configuration register) Supports MACRO facility

Facility of MACRO
New instructions, at assembler level can be created that are sequences of PIC instructions Example: macro definition
bank1 macro bsf endm status, RP0

Must be defined before use

Use: in the assembly code
bank1 ; to be replaced during assembly process

Summarizing
We have studied instruction set of PIC micro-controllers Looked at small code snippets We know about MPASM You will use these instructions for developing different applications

The PIC Family: Peripherals

Different PICs have different on-board peripherals Some common peripherals are:
Tri-state (floatable) digital I/O pins Analog to Digital Converters (ADC) Serial communications: UART (RS-232C), SPI, I2C, CAN Pulse Width Modulation (PWM) Timers and counters Watchdog timers

Interrupts: a review
An interrupt is any service request that causes the CPU to stop its current execution stream and to execute an instruction stream that services the interrupt When the CPU finishes servicing the interrupt, it returns to the original execution stream at the point where it left off. Interrupt driven I/O for interfacing with on chip peripherals

Interrupts in PIC
Sources of interrupt are many
INT pin interrupt from external source Port B change interrupt (RB7:RB4) Timer overflow interrupts USART interrupts A/D conversion interrupts LCD interrupt others

Interrupt Management
Use of register INTCON: Status and Control
Bit 7: Global interrupt enable
Enables (if set) all unmasked interrupts or disables all interrupts

Bits 6,5,4,3: For enabling peripheral, timer0, external interrupt, port B bit change interrupts respectively Bits 2,1,0 : Timer0, INT, port change interrupt flag respectively
Flag bits get set when interrupt occurs regardless of the value of enable bit

Peripheral Interrupts
Managed using PIE and PIR registers PIE registers contain bits for enabling interrupts from individual peripherals PIR registers contain flag bits for individual peripheral interrupts Bit oriented instructions can be used to examine and/or manipulate interrupt control and status registers

Interrupt Processing
When interrupt is responded to
GIE bit is cleared to disable other interrupts PC is pushed into stack PC is loaded with 0004h Save STATUS & W register in temporary memory locations In the ISR, source of interrupt is determined by polling the interrupt flag bit

Return from interrupt instruction (retfie) exits ISR, sets GIE bit to allow pending interrupt to execute

Interrupt Timing

Ref: PIC reference manual

Interrupt Constraints
Each interrupt source charaterised by
Minimum time interval between interrupts from the same source Maximum time it takes the CPU to execute interrupt sources handler

Servicing of interrupts must not be delayed beyond the limit imposed by the timing requirement of the source

Critical Region
A critical region is a sequence of instructions that must be protected from an intervening interrupt or produce erroneous output In PIC this problem is handled by
Single cycle read-modify-write instructions
xorwf PORTD,F Port D data read, XORed with W and written back to port D

Disabling interrupts by clearing GIE bit for the required set of instructions

PIC Peripherals: Digital I/O

All PICs have digital I/O pins, called Ports
the 8pin 12C508 has 1 Port with 4 digital I/O pins the 68pin 17C766 has 9 Ports with 66 digital I/O pins

Ports used to control and monitor external devices Ports have 2 control registers
TRISX sets whether each pin is an input or output PORTX sets their output bit levels

Most pins have 25mA source/sink (directly drives LEDs)

Typical Configuration: Port A

Setting a TRISA bit put output drivers in high impedance state; clearing a bit in TRISA puts contents of output latch on the pin
Ref: PIC reference manual

Example: Port A
All pins are I/O with associated direction bits in TRISA Initialisation code:
clrf STATUS clrf PORTA bsf STATUS, RP0 movlw 0xCF movlwf TRISA ;bank 0 ; initialises by clearing output latches ; select bank1 ; value used to initialise data direction ; PortA<3:0>=input, <5:4>=output

Managing port read/write

BCF/BSF PORTn does the following: Reads in the PORTn byte Clears/sets the bit Write the whole byte back. If external input pulls a different output pin low or high during the READ, the read in value will not be what you expect - WORSE, the WRITE will permanently change it that way. Solution: Use Shadowed I/O (e.g.: set PORTA Bit 0) bsf _PORTA, 0 movf _PORTA, W movwf PORTA

Synchronous Serial Port

Serial interface module for communicating with other devices or micro-controllers Module operates in one of two modes:
Serial Peripheral Interface Inter-integrated circuit (I2C)

PIC Peripherals: Timers

Available in all PICs. 14+ bit cores may generate interrupts on timer overflow. Some 8 bits, some 16 bits, some have prescalers Can use external pins as clock in/clock out

PIC Timers / Timer 0

8 bit timer/counter with prescaler Readable and writeable 8-bit software programmable prescaler
Prescaler can divide the counter input by 2,4,8,16 256

Internal or external clock set

External clock connected to bit 4 of Port A

Interrupt on overflow from 0xFF to 0x00 Edge Select for external clock

PIC Timers / Timer 1

16-bit timer/counter Interrupt on overflow Readable and writeable Different Operating modes
External crystal can be used

Programmable prescaler

Timer1: Operating Modes

Synchronised Timer
Increments every instruction cycle

Synchronised Counter
Timer increments on rising edge of external clock External clock is synchronised with internal phase clock

Asynchronous Counter
Timer increments independent of internal phase clock

Typical Application: Real-time Clock

Even when processor sleeps, timer1 continues to count in asynchronous mode, on overflow could wake-up the device

Ref: PIC reference manual

PIC Timers / Timer 2

Readable & writable 8-bit timer/counter with prescaler and postscaler Interrupt on overflow

Ref: PIC reference manual

Watchdog Timer
Free running on chip RC oscillator which does not require any external component A WDT time-out generates a device reset In sleep mode a WDT time-out causes the device to wake-up To avoid unintended device reset, postscaler has to be changed after clearing watchdog timer WDT is enabled/disabled by a device configuration bit

PIC Peripherals: CCP Modules

Capture/Compare/PWM (CCP) Each module contains a 16 bit register which can operate as 16-bit capture, 16-bit compare or as 10-bit PWM master-slave duty cycle register Capture counts external pin changes Compare will interrupt when the timer equals the value in a compare register

Capture
Capture mode records value of timer1 when events like rising edge or falling edge occurs on pin CCPx When capture is made, interrupt request flag bit is set

Compare
Content of register compared with Timer1 register pair value When match occurs, voltage level at CCPx pin is changed depending on the value of control bits

PWM
Pulse Width Modulation Duty Cycle often expressed as a percentage of the period. Average DC voltage will be approximately the same percentage of the on voltage. Typical uses:
Intensity control Motor control Temperature control

PWM Mode
In pulse width modulation mode, CCPx pin produces up to a 10-bit resolution PWM output
Since CCPx pin is multiplexed with the port data latch, the corresponding TRIS bit must be cleared

Coupled with Timer2 for producing output Period and duty cycle of timer2 output manipulated for obtaining desired PWM waveform

PWM: Block diagram

Ref: PIC reference manual

PWM: Set up
Steps required for setting up PWM
Establish the PWM period by writing to PR2 register Establish the PWM duty cycle by writing onto CCPRxL & CCPxCON<5:4> bits Make CCPx pin an output Establish TMR2 prescale value and enable timer by writing to T2CON Configure CCP module for PWM operation

PWM: A simple application

Speed control of a DC motor
Vary the Thigh and Tlow of the output waveform. When the duty ratio is changed the speed of the Motor is changed as average DC input changes

PIC Peripherals: ADCs

Converts an analog input signal to 8-bit digital value
Generates result via successive approximation

Input analog channel, Conversion clock, Analog reference voltage is software selectable Can operate even while the device in sleep mode. Can generate an interrupt on ADC conversion done
Result written on to ADRES register

More PIC Peripherals

Some devices have 8-bit parallel slave port
Multiplexed onto one of devices I/O port For interfacing with 8-bit peripherals or microprocessors

USART (universal synchronous and asynchronous receiver transmitter)

Can be configured as a full duplex channel for communication with or peripheral devices like CRT

LCD Module
Generates timing control to drive LCD panel Also provides control of pixel data

More PIC Peripherals

EEPROM data memory
Readable and writable under normal operations Not mapped directly in register file space Indirectly accessed using SFR

In-circuit programmer
Serial in-circuit programming support

PIC: Examples
Low End: 12C508
8pin package (DIP) 12bit core - 33 instructions 1us instruction time (Tclk = 4MHz) 512 12bit program memory 25 8bit data memory or registers (File registers) 2 level hardware stack (no interrupts) 5 GPIO pins, 1 input only (25mA source/sink) Features: Internal pullups, wake up on pin change, internal oscillator Peripherals: Timer, Watch Dog Timer

PIC Examples
Mid Range: 16F876
28pin package (DIP) 14bit core - 35 instructions 200ns instruction time (Tclk = 20MHz) 8,092 14bit FLASH program memory 368 8bit data memory or registers (File registers) 256 8bit EEPROM (nonvolatile) data registers 8 level hardware stack (interrupts enabled) 22 GPIO (20mA source / 25mA 7sink) Peripherals: 5ch 10bit ADC, USART/I2C/SPI, 16bit & 8bit timers Features: Brown out detect, In-Circuit Debugger (ICD)

Summary
We have studied PIC family of processors
Architecture Instruction set Peripherals

PIC processors are well suited for lowend and mid-range applications