The Introduction of PCI Bus

Reference: 1.Specification Industrial PCI Bus V1.52, SIPS(Standard Industrial Pc Systems) Oct. 1998 2.PC/104-ISA to PCI , Marc F. Brown,Adastra systems Corp.-Wescon/98 , 1998 3.URL:www.Intel.com

Outline
Cost-Effective Technology PCI ARBITER PCI Power Supply PC Bus Comparison Evolving to Meet Industry Needs

 In 1992,the Peripheral Component Interconnect(PCI) bus was released. Introduced by Intel as an open architecture,it quickly became the standard for high-speed buses in the PC markets. PCI standards addressing the usage of one of two high speed buses,either a 32-bits or a 64-bits,operating at bus speeds of up to 33MHz,or 66MHz respectively. A PCI normally operates in a master mode(initiator in PCI terminology) and slave mode(target in PCI terminology).

Cost-Effective Technology
PCIs standardized components and silicon have enabled huge economies of scale that make PCI products easy and inexpensive to develop. As a result,PCI has become the universal connection standard,and has given PCs an affordable graphics capability that was unachievable with previous bus technologies.

 PCIs standardized components and silicon have enabled huge economies of scale that make PCI products easy and inexpensive to develop. As a result,PCI has become the universal connection standard,and has given PCs an affordable graphics capability that was unachievable with previous bus technologies.

 The hidden bus arbitration reduces latency,increasing bus efficiency(e.g. bus master component requesting the bus while another is transferring data.) PCI bridge allows disciplined transfer of data between computer buses of different protocols and bandwidth.

PC Bus Comparison

Evolving to Meet Industry Needs

Recent enhancement to PCI version 2.2 include: PCI Hot-Plug: Enables removal or replacement of adapter cards without having to shut down the main system,so the PCI cards are Hot-Plug capable without modification. PCI Power Management: The power manages by o.s. PCI Power Management enables energy conservation in PCs,efficient mobile computing,and higher-availability PCs for off-hours tasks such as receiving faxes or Internet transmissions.

Functional Diagram of a Computer Bus

PCI Bus Arbiter for Video codec

Design of PCI Arbiter

1. Video Grabber (VG) 2. Video Codec (VC) 3. Fire Wire (FW) 4. Video Grabber 5. Video Codec 6. CPU (Host)

 Video Grabber, which will input a raw video data. It can be NTSC, PAL or SECAM sequence or may be in XGA, SVGA or in any other format. Any color motion picture can be processed, say, at 30 frames per second or 25 frames per second. Using the PCI, we can input the raw data into the Video Codec. Video Codec brings about the compression and reconstruction. We have an encoder and a decoder in the Codec, which brings about respectively the compression and decompression. This has to be designed in Verilog and implemented on either FPGA or ASIC. Fire Wire is a serial bus, which can be connected up to 64K nodes. It serializes the compressed data and broadcasts the compressed bit stream. Concurrently, it can receive a compressed bit stream from external source and send it to the decoder in Video Codec for effecting decompression. CPU (PC), which configures and coordinates the system activities via a north bridge

Arbitration process

Timing diagram

VERILOG CODE FOR PCI Arbiter Design

The PCI arbiter design code is presented in Verilog_code_13.1. The design module is named pci_arbiter. After declaring the design module, the inputs/outputs are identified. The arbiter design is a simple FSM and is realized using the case statement. All the conditional states of the request and grant signals are coded in the same order as the ASM chart and are self-explanatory. The states of the ASM chart are identified by the signal, arbiter_state, in the code. Priority is automatically assigned since we have used ifelse ifelse structure in the code. module pci_arbiter ( // Declare the design module

clk, // List I/Os. reset_n, REQ0, REQ1, REQ2, REQ3, GNT0, GNT1, GNT2, GNT3 );

input clk ; // Declare the inputs input reset_n ; // and outputs of the input REQ0 ; // module. input REQ1 ; input REQ2 ; input REQ3 ; output GNT0 ; output GNT1 ; output GNT2 ; output GNT3 ;

reg GNT0 ; // Declare outputs as registers. reg GNT1 ; reg GNT2 ; reg GNT3 ; reg [2:0] arbiter_state ; // State declaration. always @ (posedge clk or negedge reset_n) begin if (reset_n == 0) begin // Switch OFF all grant signals to start with

GNT0 <= 0 ; GNT1 <= 0 ; GNT2 <= 0 ; GNT3 <= 0 ; arbiter_state <= 0 ; // Initialize the state when the system is reset. End else case (arbiter_state) 0:

begin // Wait state. // Switch OFF all grants signals. GNT0 <= 0 ; GNT1 <= 0 ; GNT2 <= 0 ; GNT3 <= 0 ; if (REQ0 == 1) // If Video Grabber request is asserted, // go to the Video Grabber state 1.

arbiter_state <= 1 ; // Otherwise, go to the Video Codec, state 2. else if (REQ1 == 1) arbiter_state <= 2 ; // Otherwise, go to the Fire Wire, state 3. else if (REQ2 == 1) arbiter_state <= 3 ; // Otherwise, go to the Host (CPU), state 4. else if (REQ3 == 1) arbiter_state <= 4 ;

// Otherwise, go to the WAIT, state 0. else arbiter_state <= 0 ; end 1: begin // Switch OFF all grant signals // except that of Video Grabber. GNT0 <= 1 ; GNT1 <= 0 ; GNT2 <= 0 ; GNT3 <= 0 ; if (REQ0 == 1)

// If Video Grabber request is still asserted, // remain in the Video Grabber state 1. arbiter_state <= 1 ; // Otherwise, go to the Video Codec, state 2. else if (REQ1 == 1) arbiter_state <= 2 ; // Otherwise, go to the Fire Wire, state 3. else if (REQ2 == 1) arbiter_state <= 3 ; // Otherwise, go to the Host (CPU), state 4. else if (REQ3 == 1) arbiter_state <= 4 ;

// Otherwise, go to the VG, state 1. else arbiter_state <= 1 ; end 2: begin // Switch OFF all grant signals // except that of Video Codec. GNT0 <= 0 ; GNT1 <= 1 ; GNT2 <= 0 ; GNT3 <= 0 ; if (REQ1 == 1) // If Video Codec request is still asserted, remain in the Video Codec state 2. arbiter_state <= 2 ;

// Otherwise, go to the Fire Wire state 3. else if (REQ2 == 1) arbiter_state <= 3 ; // Otherwise, go to the CPU state 4. else if (REQ3 == 1) arbiter_state <= 4 ; // Otherwise, go to the VG state 1. else arbiter_state <= 1 ; end 3: begin // Switch OFF all grant signals except Fire Wire. GNT0 <= 0 ; GNT1 <= 0 ; GNT2 <= 1 ; GNT3 <= 0 ; if (REQ2 == 1)

 // If Fire Wire request is still asserted, remain in the Fire Wire state 3. arbiter_state <= 3 ; // Otherwise, go to the Video Grabber, state 1. else if (REQ0 == 1) arbiter_state <= 1 ; // Otherwise, go to the Video Codec, state 2. else if (REQ1 == 1) arbiter_state <= 2 ; // Otherwise, go to the Host (CPU), state 4. else if (REQ3 == 1) arbiter_state <= 4 ; // Otherwise, go to the VG state 1.

else arbiter_state <= 1 ; end 4: begin // Switch OFF all grant signals except // that for the Host. GNT0 <= 0 ; GNT1 <= 0 ; GNT2 <= 0 ; GNT3 <= 1 ; if (REQ3 == 1) // If CPU request is still asserted, remain in the CPU state 4. arbiter_state <= 4 ; // Otherwise, go to the VG state 1. else arbiter_state <= 1 ; end default: arbiter_state <= 0 ; // Otherwise, remain in the WAIT state. endcase end endmodule

Simulation Results of back annotated PCI Arbiter