Computer Systems and Device

Management

Fred Kuhns
fredk@cse.wustl.edu
Applied Research Laboratory,
Department of Computer Science and Engineering,
Washington University in St. Louis

Washington
WASHINGTON UNIVERSITY IN ST LOUIS
 OS Organization
Operating System
File
Process & Resource Manager
Manager

Memory Device
Manager Manager

Processor(s) Main Memory Devices

Hardware

Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 2

 OS Techniques
• Controlling access to hardware resources is done using
hardware supported privilege levels, typically two: user
and system

• Privileged operations, resource management, protection

enforcement (isolation), and sharing performed by a
trusted control program: the Kernel

• Users request OS services using a well defined interface

that validates user and notifies OS of request: two
common methods:
– System calls: trap changes mode and executes privileged code in
context of calling process
– Message passing: interface constructs message and sends to
another system (i.e. privileged) process
Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 3
 System Call – Traditional Monolithic Kernel
execution environment
application
trap libraries
user
System call interface
kernel System Services
File subsystem
dispatcher IPC
Process
Exceptions

Buffer cache control Scheduler

Interrupt

subsystem
char block Memory
Device drivers

hardware
Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 4
 Message Passing – Micro-Kernel

Client DB server

Task mngr I/O mngr Memory mngr

microkernel

Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 5

 Von Neumann Architecture

Central Processing Unit (CPU)

Arithmetic-Logical Unit
(ALU) Control Unit

Device Controller
Primary Memory Device Controller
Device
Device Controller
Device
Device Controller
Device
Device

Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 6

An Example: Port Processors for an IP Router
Control
Processor
ATM Switch Core

Switch Fabric
OPP

OPP
OPP

OPP

OPP

OPP
IPP

IPP

IPP
IPP

IPP

IPP
Processors

FPX FPX FPX FPX FPX FPX

Port

SPC SPC SPC SPC SPC SPC

LC LC LC LC LC LC
Line Cards (link interfaces)
Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 7
Functional Diagram of the Port Processor (SPC)

Control
Processor

Switch Fabric

SPC SPC
Dist. Q. Ctl. Dist. Q. Ctl. Dist. Q. Ctl. Dist. Q. Ctl.

Flow Output Input Flow

Lookup Port Port Lookup
. . .
Proc. Proc.

Flow/Route Flow/Route
Lookup Lookup

Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 8

The Smart Port Card: an embedded processor
Switch Interface

DRAM

Link Interface
APIC CPU Module

PCI Bus

System FPGA
Serial Ports

Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 9

 Typical Pentium PC Architecture
Addr/Data Ctrl

Ctrl
North­
Cache CPU DRAM
Bridge Addr/Data/Ctrl

PCI Bus
Intr
NMI
INIT

PCI
SouthBridge (PIIX3) Devices
(PIC, PIT, …)
ISA Bus

ISA Super­IO BIOS

Devices
Kbd/Mse

Parallel
Floppy
Uarts
RTC

...

Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 10

 Zooming in on Computer Architecture
CPU Memory 0
PC .. 1
IR MAR .
Reg N
Reg 1 MBR Instruction
Reg 0
I/O AR
Instruction
execution Instruction
..
unit I/O BR
.
Data
Devices
Data
Data
.. Data
..
Buffers .
N
PC - Program Counter MBR - Memory Buffer Register
IR - Instruction Register I/O AR - Input/Output Address Register
MAR - Memory Address Register I/O BE - Input/Output Buffer Register
Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 11
 Processor Registers
• User-visible registers
– Enable programmer to minimize main-memory
references by optimizing register use

• Control and status registers

– Used by processor to control operation of the
processor
– Used by operating-system routines to control the
execution of programs

Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 12

 User-Visible Registers

• May be referenced by machine language

• Available to all programs - application programs

and system programs

• Types of registers
– Data - can be assigned by the programmer
– Address - contain main memory address of data and
instructions. Or may contain a portion of an address that
is used to calculate the complete address.
– Condition Code or flags

Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 13

 Control and Status Registers

• Program Counter (PC)

– Contains the address of an instruction to be fetched

• Instruction Register (IR)

– Contains the instruction most recently fetched

• Program Status Word (PSW)

– condition codes
– Interrupt enable/disable
– Supervisor/user mode

Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 14

 Instruction Cycle
• Processor fetches instruction from memory

• PC contains address of next instruction to be fetched

• PC incremented after each fetch

Fetch Cycle Execute Cycle

Fetch Next Execute

START HALT
Instruction Instruction

Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 15

 Modern Instruction Cycle

• (a) A three-stage pipeline

• (b) A superscalar CPU
(Stallings, Operating Systems, 4th Edition)

Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 16

 Example of Program Execution
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 300 PC 300 1 9 4 0
301 5 9 4 1 301 5 9 4 1 301 PC
302 2 9 4 1 AC 302 2 9 4 1 0003 AC
1940 IR 1940 IR
940 0003 940 0 0 0 3
941 0002 941 0 0 0 2 1 - load
Step 1 Step 2
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 301 PC 300 1 9 4 0
301 5 9 4 1 301 5 9 4 1 302 PC
302 2 9 4 1 0003 AC 302 2 9 4 1 0005 AC
5941 IR 5941 IR
940 0003 940 0 0 0 3
941 0002 941 0 0 0 2
3+2=5
Step 3 Step 4 5 - add
Memory CPU Registers Memory
300 1940 CPU Registers
301 302 PC 300 1 9 4 0
5941 301 5 9 4 1 303 PC
302 2941 0005 AC 302 2 9 4 1
0005 AC
2941 IR
940 0003 940 0 0 0 3 2941 IR
941 0002 941 0 0 0 5
2 - store
Step 5 Step 6
Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 17
Interrupts – devices notify CPU of some event

Processor
Device table
dispatcher clock handler
(interrupt handler) X

Bus

command status rt-counter

Timer

Interrupt is generated every 10ms, used by OS for

accounting and resource (CPU)
sharing.

Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 18

 Instruction Cycle with Interrupts

Fetch Cycle Execute Cycle Interrupt Cycle

Interrupts
Disabled

Interrupts
Enabled
Fetch Next Execute Check for &
START
Instruction Instruction Process Int

HALT

Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 19

 Interrupt Cycle
1. Processor checks for interrupts

3. If no interrupts fetch the next instruction for the

current program

5. If an interrupt is pending
– save current PC value
– set PC to start of dispatcher

• System interrupt dispatcher saves some general

purpose registers, determines interrupt type (or id)
and calls handler by indexing into an array of function
pointers.
Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 20
 Simple Interrupt Processing
Hardware Software
Device controller or
other system hardware
issues an interrupt Save remainder of
process state
Processor finishes information
execution of current
instruction

Process interrupt
Processor signals
acknowledgment
of interrupt

Restore process state

Processor pushes PSW information
and PC onto control
stack

Restore old PSW

Processor loads new
and PC
PC value based on
interrupt

Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 21

 What about Multiple Interrupts
Simple Approach - disable interrupts

3. Use Priorities to differentiate between interrupt

classes, run the highest priority pending interrupt.

5. Disable interrupts so processor can complete task

7. Interrupts remain pending until the processor enables

interrupts

9. After interrupt handler routine completes, the

processor checks for additional interrupts
Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 22
 I/O and Devices
Processor
Device table
dispatcher Device Driver
(interrupt handler) X

Bus

command status data 0

data 1
Device Controller
(firmware and logic) ...
Device X data N-1

Fred Kuhns (01/17/09) CS422 – Operating Systems Concepts 23