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CEERI Profile VLSI Technology Scaling HDL What is VHDL ? Describing in Design Structure of Entity Design methodologies of digital design Simulation cycle Sequential circuit block diagram
CEERI PROFILE
ABOUT CEERI:: Central Electronics Engineering Research Institute (CEERI), Pilani, is a pioneer research institute in the country and a constitute laboratory of council of scientific and industrial research (CSIR), New Delhi, established in 1953, for advance research and development (R&D) in the field of electronics.
FOLLOWING THREE MAJOR AREAS:Microwave tubes Semiconductor devices Electronic system
Improvement in manufacturing lead to ever smaller transistors allowing more per chip. >107 gates/chip now possible;doubles every 18 months or so
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Variety of logic families
TTL(Transistor-Transistor Logic)
CMOS(Complementary Metal Oxide Semiconductor) ECL(Emitter Coupled Logic) GaAs(Gallium Arsenide)
VHDL(Very High Speed Integrated Circuits Hardware Description Languages) Developed by DOD from 1983 IEEE Standard 1076-1987/1993/200x Based on the ADA language
Verilog IEEE Standard 1364-1995/2001/2005 Based on the C Language
WHAT IS VHDL
VHDL is an acronym for VHSIC Hardware Description Language (VHSIC is an acronym for Very High Speed Integrated Circuits).
It is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field programmable gate arrays and integrated circuits. The language has constructs that enable to express the concurrent or sequential behavior of a digital system with or without timing. This language not only defines the syntax but also define very clear simulation semantics for each language construct.
DESCRIBING A DESIGN
In VHDL, a design consists at a minimum of an entity which describes the interface and an architecture which contains the actual implementation An entity can be described using, 1. Entity declaration. 2. Architecture. 3. Configuration 4. Package declaration.
5. Package body.
Entity declaration: It defines the names, input output signals and modes of a hardware module. Architecture: It describes the internal description of design or it tells what is there inside design. Configuration: If an entity contains many architectures and any one of the possible architecture binding with its entity is done using configuration.
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Package declaration: Package declaration is used to declare components, types constants, functions and so on Package body: A package body is used to declare the definitions and procedures that are declared in corresponding package. Values can be assigned to constants declared in package in package body.
STRUCTURE OF AN ENTITY
CONTINUE
. Zout <=IN1; else if (S1=0 and S0=1) Zout<=IN2; else (S1=1 and S0=0) Zout<=IN3; else Zout<=IN4; end if; end process; end BEH ;
MUX 4:1
SIMULATION CYCLE
Start Simulation
Update Signal
Evaluate Model
End Simulation
ADVANTAGES OF VHDL
VHDL offers several advantages to the designer.
Standard language.
Readily available tools. Powerful and versatile description language. Multiple mechanisms to support design hierarchy. Versatile design reconfiguration support. Support for multiple levels of abstraction.
CONCLUSION
I conclude that the VHDL language is more comprehensive and simple. As a knowledge of Hardware Description Language has become a very important aspect for ELECTRONICS AND COMMUNICATION ENGINEERING students. Moreover with the advent of new technology every 5 to 6 months, it has become very important to know the various technology advancements happening in electronics field, and for this the Hardware Modeling Language provide a very convenient platform.
QUESTION????