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  • Built-In Self Test (BIST)

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    rajukumar25
    21 просмотров42 страницы
    Built-In Self Test (BIST) is a set of "optimal" test patterns, usually derived from fault simulation. The content of the LFSR is the remainder of the division operation.

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    Оригинальное название

    3 Bist

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    Built-In Self Test (BIST) is a set of "optimal" test patterns, usually derived from fault simulation. The content of the LFSR is the remainder of the division operation.

    Авторское право:

    Attribution Non-Commercial (BY-NC)
    Скачайте в формате PPT, PDF, TXT или читайте онлайн в Scribd
    Отметить как неприемлемый контент
    21 просмотров42 страницы

    Built-In Self Test (BIST)

    Загружено:

    rajukumar25
    Built-In Self Test (BIST) is a set of "optimal" test patterns, usually derived from fault simulation. The content of the LFSR is the remainder of the division operation.

    Авторское право:

    Attribution Non-Commercial (BY-NC)
    Скачайте в формате PPT, PDF, TXT или читайте онлайн в Scribd
    Отметить как неприемлемый контент
    из 42

    Built-In Self Test (BIST)

    Built-In Self Test (BIST) Outline

    1. Introduction 2. Pattern Generation 3. Signature Analysis 4. BIST Architectures 5. Summary

    Built-In Self Test (BIST)

    1. Introduction 2. Pattern Generation 3. Signature Analysis 4. BIST Architectures 5. Summary

    Built-In Self Test (BIST)

    1. Introduction

    Built-In Self Test (BIST)

    1. Introduction General Structure

    Built-In Self Test (BIST)

    1. Introduction General Structure


    Reference Unit Under Test

    Data Generator

    Data Compressor

    Comparator

    Display BIST Controller

    Start/Stop

    Ready

    Electronic System

    Built-In Self Test (BIST)

    1. Introduction

    Built-In Self Test (BIST)

    1. Introduction

    Built-In Self Test (BIST)

    1. Introduction

    Built-In Self Test (BIST)

    1. Introduction 2. Pattern Generation 3. Signature Analysis 4. BIST Architectures 5. Summary

    Built-In Self Test (BIST)

    2. Pattern Generation

    Built-In Self Test (BIST)

    2. Pattern Generation

    Built-In Self Test (BIST)

    2. Pattern Generation

    Built-In Self Test (BIST)

    2. Pattern Generation

    Built-In Self Test (BIST)

    2. Pattern Generation

    A fixed set of optimal test patterns, usually derived from fault simulation, is used.

    Built-In Self Test (BIST)

    2. Pattern Generation

    Built-In Self Test (BIST)

    2. Pattern Generation

    Built-In Self Test (BIST)

    2. Pattern Generation

    Built-In Self Test (BIST)

    2. Pattern Generation

    Built-In Self Test (BIST)

    2. Pattern Generation

    Pseudo-Random Generation using LFSR

    Built-In Self Test (BIST)

    2. Pattern Generation

    Pseudo-Random Generation using LFSR

    Example of a 4-bit LFSR as a Pattern Generator.

    Pseudorandom states generated by the LFSR.

    Built-In Self Test (BIST)

    1. Introduction 2. Pattern Generation 3. Signature Analysis 4. BIST Architectures 5. Summary

    Built-In Self Test (BIST)

    3. Signature Analysis

    Built-In Self Test (BIST)

    3. Signature Analysis

    Steps for Response Evaluation: 1


    Methods for Response Evaluation

    2 3

    Built-In Self Test (BIST)

    3. Signature Analysis
    Serial

    r-Bit (Internal XOR) Signature Generator.


    The content of the LFSR is the remainder of the division operation.

    Built-In Self Test (BIST)

    3. Signature Analysis
    Serial

    r-Bit (External XOR) Signature Generator.


    The content of the LFSR is not the remainder of the division operation.

    Built-In Self Test (BIST)

    3. Signature Analysis
    Serial

    Example of a 4-bit (External) Signature Generator.

    Built-In Self Test (BIST)

    3. Signature Analysis
    Parallel

    r-Bit (Internal XOR) Parallel Signature Generator.

    r-Bit (External XOR) Parallel Signature Generator.

    Built-In Self Test (BIST)

    3. Signature Analysis
    Problem:

    When compacting results, there is a probability of fault masking ! Probability of failing to detect an error in the response sequence:
    Serial input
    Parallel input

    k-r k

    mL- r mL

    2 1
    Where: K: length of the sequence (# of bits) r: length of the LFRS (# of bits)

    Where: L: length of the sequence (# of test vectors) m: length of a vector (# of bits) r: length of the LFRS (# of bits)

    Built-In Self Test (BIST)

    3. Signature Analysis Modular LFSR Serial Compacter Example

    Built-In Self Test (BIST)

    3. Signature Analysis Modular LFSR Parallel Compacter Example

    Built-In Self Test (BIST)

    1. Introduction 2. Pattern Generation 3. Signature Analysis 4. BIST Architectures 5. Summary

    Built-In Self Test (BIST)

    4. BIST Architectures
    Built-In Logic Block Observer (BILBO)

    Built-In Self Test (BIST)

    4. BIST Architectures

    Built-In Self Test (BIST)

    4. BIST Architectures
    Built-In Logic Block Observer (BILBO)

    Modular Bus-Oriented Design with BILBO.

    Built-In Self Test (BIST)

    4. BIST Architectures

    Built-In Self Test (BIST)

    4. BIST Architectures
    General Form of a BILBO

    Built-In Self Test (BIST)

    4. BIST Architectures
    Example: 8-bit-Length Datapath

    Built-In Self Test (BIST)

    4. BIST Architectures
    Example: 8-bit-Length Datapath

    Built-In Self Test (BIST)

    4. BIST Architectures
    Example: 8-bit-Length Datapath

    Built-In Self Test (BIST)

    1. Introduction 2. Pattern Generation 3. Signature Analysis 4. BIST Architectures 5. Summary

    Built-In Self Test (BIST)

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