SEQUENTIAL CIRCUITS

In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on the past history of its inputs.

Introduction
A sequential circuit consists of a feedback
Combinational outputs Memory outputs

path, and employs some memory elements.

Combinational logic

Memory elements

External inputs

Sequential circuit = Combinational logic + Memory Elements

Introduction 2

Introduction
There are two types of sequential circuits:
synchronous: outputs change only at specific

time asynchronous: outputs change at any time

Bistable logic devices: latches and flip-flops. Latches and flip-flops differ in the method used
for changing their state.

Introduction

Memory Elements
Memory element: a device which can remember
value indefinitely, or change value on command from its inputs.
command Memory element Q stored value

Characteristic table:
Command (at time t) Set Reset Memorise / No Change Q(t) X X 0 1 Q(t+1) 1 0 0 1
4

Q(t): current state Q(t+1) or Q+: next state

Memory Elements

Memory Elements
Memory element with clock. Flip-flops are memory
elements that change state on clock signals.
command

Memory element

Q stored value

clock

Clock is usually a square wave.

Positive pulses

Positive edges

Negative edges

Memory Elements

Memory Elements
Two types of triggering/activation:
pulse-triggered edge-triggered

Pulse-triggered
latches ON = 1, OFF = 0

Edge-triggered
flip-flops positive edge-triggered (ON = from 0 to 1; OFF = other

time) negative edge-triggered (ON = from 1 to 0; OFF = other time)

Memory Elements

S-R Latch
Complementary outputs: Q and Q'. When Q is HIGH, the latch is in SET state. When Q is LOW, the latch is in RESET state. For active-HIGH input S-R latch (also known as NOR
gate latch), R=HIGH (and S=LOW) a RESET state S=HIGH (and R=LOW) a SET state both inputs LOW a no change both inputs HIGH a Q and Q' both LOW (invalid)!

S R
S-R Latch

Q Q
7

S-R Latch
For active-LOW input S'-R' latch (also known as
NAND gate latch), R'=LOW (and S'=HIGH) a RESET state S'=LOW (and R'=HIGH) a SET state both inputs HIGH a no change both inputs LOW a Q and Q' both HIGH (invalid)!

Drawback of S-R latch: invalid condition

exists and must be avoided.

S-R Latch

S-R Latch
Characteristics table for active-high input S-R latch:
S 0 1 0 1 R 0 0 1 1 Q NC 1 0 0 Q' NC 0 1 0 No change. Latch remained in present state. Latch SET. Latch RESET. Invalid condition.

S R

Q Q'

Characteristics table for active-low input S'-R' latch:

S' 1 0 1 0 R' 1 1 0 0 Q NC 1 0 1 Q' NC 0 1 1 No change. Latch remained in present state. Latch SET. Latch RESET. Invalid condition.

S R

Q Q'

S-R Latch

S-R Latch
Active-HIGH input S-R latch
10 100 R Q 11000 Q' 0 0 1 1 0
S 1 0 0 0 1 R 0 0 1 0 1 Q Q' 1 0 initial 1 0 (afer S=1, R=0) 0 1 0 1 (after S=0, R=1) 0 0 invalid!

10 001 S

Active-LOW input S-R latch

S' Q Q S' ' Q Q'
S-R Latch

R'

R'

S' R' 1 0 1 1 0 1 1 1 0 0

Q Q' 0 1 initial 0 1 (afer S'=1, R'=0) 1 0 1 0 (after S'=0, R'=1) 1 1 invalid!

10

Gated S-R Latch

S-R latch + enable input (EN) and 2 NAND
gates gated S-R latch.
S EN Q' R Q

S EN R

Q'

Gated S-R Latch

11

Gated S-R Latch

Outputs change (if necessary) only when EN is
HIGH. Under what condition does the invalid state occur? Characteristic table:
EN=1
Q(t) 0 0 0 0 1 1 1 1 S 0 0 1 1 0 0 1 1 R 0 1 0 1 0 1 0 1 Q(t+1) 0 0 1 indeterminate 1 0 1 indeterminate

S R 0 0 1 1 0 1 0 1

Q(t+1) Q(t) No change 0 Reset 1 Set indeterminate

Q(t+1) = S + R'.Q S.R = 0

Gated S-R Latch

12

JK latch
The JK latch is an SR latch that is made to toggle its output when passed the restricted combination of 11
JK latch J K Qnext Comment No change Reset Set Toggle

0 0 Q 0 1 0 1 0 1 1 1 Q

Gated D Latch
Make R input equal to S' gated D latch. D latch eliminates the undesirable condition
of invalid state in the S-R latch.
D EN Q' Q

D EN

Q
Q'

Gated D Latch

14

Gated D Latch
When EN is HIGH,
D=HIGH latch is SET D=LOW latch is RESET

Hence when EN is HIGH, Q follows the D (data)

input. Characteristic table:

EN 1 1 0 D 0 1 X

Q(t+1) 0 1 Q(t) Reset Set No change

When EN=1, Q(t+1) = D

Gated D Latch

15

Latch Circuits: Not Suitable

Latch circuits are not suitable in synchronous logic

circuits. When the enable signal is active, the excitation inputs are gated directly to the output Q. Thus, any change in the excitation input immediately causes a change in the latch output. The problem is solved by using a special timing control signal called a clock to restrict the times at which the states of the memory elements may change. This leads us to the edge-triggered memory elements called flip-flops.
Gated D Latch 16

Edge-Triggered Flip-flops
Flip-flops: synchronous bistable devices Output changes state at a specified point on a
triggering input called the clock. Change state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock signal.
Clock signal
Positive edges Negative edges

Edge-Triggered Flip-flops

17

Edge-Triggered Flip-flops
S-R, D and J-K edge-triggered flip-flops. Note
the > symbol at the clock input.
S C R Q Q' D C Q Q' J C K Q Q'

Positive edge-triggered flip-flops

S C R D C J C K

Q'

Q'

Q'

Negative edge-triggered flip-flops

Edge-Triggered Flip-flops

18

S-R Flip-flop
S-R flip-flop: on the triggering edge of the clock
pulse,
S=HIGH (and R=LOW) a SET state R=HIGH (and S=LOW) a RESET state both inputs LOW a no change both inputs HIGH a invalid

Characteristic table of positive edge-triggered S-R

flip-flop:
S 0 0 1 1 R 0 1 0 1 CLK X Q(t+1) Q(t) 0 1 ? Comments No change Reset Set Invalid

X = irrelevant (dont care) = clock transition LOW to HIGH

SR Flip-flop 19

S-R Flip-flop
It comprises 3 parts:
a basic NAND latch a pulse-steering circuit a pulse transition detector (or edge detector) circuit

The pulse transition detector detects a rising (or

falling) edge and produces a very short-duration spike.

SR Flip-flop

20

S-R Flip-flop
The pulse transition detector.
S CLK Pulse transitio n detector R

Q
Q'

CLK CLK CLK' CLK*

CLK'
CLK*

CLK CLK CLK' CLK*

CLK'
CLK*

Positive-going transition (rising edge)

SR Flip-flop

Negative-going transition (falling edge)

21

D Flip-flop
D flip-flop: single input D (data)
D=HIGH a SET state D=LOW a RESET state

Q follows D at the clock edge. Convert S-R flip-flop into a D flip-flop: add an inverter.
D CLK S C R Q Q'
D 1 0 CLK Q(t+1) 1 0 Comments Set Reset

A positive edge-triggered D flip-flop formed with an S-R flip-flop.

= clock transition LOW to HIGH

D Flip-flop

22

D Flip-flop
Application: Parallel data transfer.
To transfer logic-circuit outputs X, Y, Z to flipflops Q1, Q2 and Q3 for storage.
D X
Combinational logic circuit

Q Q' Q Q'

CLK D CLK

Q1 = X*

Y Z

Q2 = Y*

D
Transfer CLK

Q3 = Z*

Q' * After occurrence of negative-going transition

D Flip-flop 23

J-K Flip-flop
J-K flip-flop: Q and Q' are fed back to the pulsesteering NAND gates. No invalid state. Include a toggle state.

J=HIGH (and K=LOW) a SET state K=HIGH (and J=LOW) a RESET state both inputs LOW a no change both inputs HIGH a toggle

J-K Flip-Ffop

24

J-K Flip-flop
J-K flip-flop.
J CLK K Pulse transition detector Q Q'

Characteristic table.
Q J K 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Q(t+1) 0 0 1 1 1 0 1 0
25

J 0 0 1 1

K 0 1 0 1

CLK

Q(t+1) Q(t) 0 1 Q(t)'

Comments No change Reset Set Toggle

Q(t+1) = J.Q' + K'.Q

J-K Flip-flop

0 0 0 0 1 1 1 1

T Flip-flop
T flip-flop: single-input version of the J-K flip flop,
formed by tying both inputs together.
T CLK Pulse transition detector Q
CLK T J C K Q Q'

Q'

Characteristic table.
T 0 1 CLK Q(t+1) Q(t) Q(t)' Comments No change Toggle
Q T 0 0 1 1 0 1 0 1 Q(t+1) 0 1 1 0

Q(t+1) = T.Q' + T'.Q

T Flip-flop 26

T Flip-flop
Application: Frequency division.
High J CLK C K CLK Q CLK QA QB
Divide clock frequency by 2. Divide clock frequency by 4.

High Q CLK J C K QA

High J C K QB

T Flip-flop

27

Asynchronous Inputs
S-R, D and J-K inputs are synchronous inputs, as
data on these inputs are transferred to the flipflops output only on the triggered edge of the clock pulse. Asynchronous inputs affect the state of the flip-flop independent of the clock; example: preset (PRE) and clear (CLR) [or direct set (SD) and direct reset (RD)] When PRE=HIGH, Q is immediately set to HIGH. When CLR=HIGH, Q is immediately cleared to LOW. Flip-flop in normal operation mode when both PRE and CLR are LOW.

Asynchronous Inputs

28

Asynchronous Inputs
A J-K flip-flop with active-LOW preset and clear
inputs.PRE
J C K

PRE J
Q

CLK
Q'

Pulse transition detector

K
CLR

Q'

CLR CLK

PRE
J = K = HIGH CLR Q

Preset
Asynchronous Inputs

Toggle

Clear
29

SR Master-Slave Flip-Flop
Read input at first half of clock cycle Output only changed at second half of clock cycle The value that is produced at the output is the response of the value that is stored in the master stage immediately before negative edge occurred.
S C Master S C Y Slave S C Q

Y
R R

From Figure 5-9, page 216

 Master slave structure provides following functionalities to the logic:

The output may only change once The change in the output is triggered at negative edge of clock The change may occur during negative clock only

Shift Registers

Registers 1.33

Shift Register Applications

Shift Registers are an important Flip-Flop configuration with a wide range of applications, including:

Computer and Data Communications Serial and Parallel Communications Multi-bit number storage Sequencing Basic arithmetic such as scaling (a serial shift to the left or right will change the value of a binary number a power of 2) Logical operations
Registers 1.34

Parallel versus Serial

Serial communications: provides a binary number as a sequence of binary digits, one after another, through one data line.

Parallel communications: provides a binary number as binary digits through multiple data lines at the same time.

Registers 1.35

Shift Registers
Shift Registers are devices that store and move data bits in serial (to the left or the right),

..or in parallel,

..or a combination of serial and parallel.

Registers 1.36

Configuration
In Shift Registers, the binary digit transfers (shifts) from the output of one flip-flop to the input of the next individual Flip-Flop at every clock edge. Once the binary digits are shifted in, the individual Flip-Flops will each retain a bit, and the whole configuration will retain a binary number.

Registers 1.37

Construction
Shift registers are constructed from flip-flops due to their characteristics:
Edge-triggered devices Output state retention

Each Flip-Flop in a shift register can retain one binary digit.

For instance, if a 5-bit binary number needs to be stored and shifted, 5 flip-flops are required.

Each binary digit transfer operation requires a clock edge. Asynchronous inputs are useful in resetting the whole configuration.

Registers 1.38

Shift Register Construction

Shift registers are comprised of D Flip-Flops that share a common clock input.
D Q Q D Q Q D Q Q

Registers 1.39

Combinations of Data Transfer Methods

SISO: Serial In, Serial Out
10110 10110 10110

SIPO: Serial In, Parallel Out

10110

10110

PISO: Parallel In, Serial Out

10110 10110

PIPO: Parallel In, Parallel Out

10110 How many clock edges are required for each operation?
Registers 1.40

SISO Flip-Flop Shift Register

a Serial In Serial Out shift register has a single input and a single output
Input

D Q Q

D Q Q

D Q Q

Output

Registers 1.41

SIPO Flip-Flop Shift Register

a Serial In Parallel Out shift register has a single input and access to all outputs
Output Output Output

Input

D Q Q

D Q Q

D Q Q

Registers 1.42

PISO Flip-Flop Shift Register

a Parallel In Serial Out shift register requires additional gates, and the parallel input must revert to logic low. Input
Input Input Output

D Q Q

D Q Q

D Q Q

Registers 1.43

PISO Flip-Flop Shift Register

PIPO Flip-Flop Shift Register

a Parallel In Parallel Out register has the simplest configuration. It represents a memory device.Input Input Input
D Q Q D Q Q D Q Q

Output

Output

Output

Registers 1.45

Application: Parallel transferring the contents of a Register to another register.

Describe where this circuit combination may be used.

Registers 1.46

Bidirectional Shift register

A binary number can be divided by 2 by shifting it one stage to the right similarly number can be multiplied by 2 by shifting it to the left A bidirectional, or reversible, shift register is one in which the data can be shift either left or right

JK Shift Registers
J-K Shift registers are seldom used, as two inputs (J,K) are required to load the first flip-flop (note all others receive only set or reset inputs).

Input

Output

Input

Registers 1.48

Ring Counter
A ring counter takes the serial output of the last Flip-Flop of a shift register and provides it to the serial input of the first Flip-Flop.

Ring Counters are also known as re-circulating shift registers.

Registers 1.49

Ring Counter

with initial register values of 100, the repeating pattern is: 100, 010, 001, 100... .

Registers 1.50

Self-Starting or Load on Power-up

Note that one of the registers must be preloaded with a 1 (or 0) in order to operate properly.

Registers 1.51

Johnson Counter
A Johnson Counter re-circulates the last flip-flop Q (inverted) output back to the input of the first Flip-Flop. It doesnt require an initialization value, and will provide a predictable output state sequence.

Registers 1.52

Re-Circulating Counters
A 4-bit Johnson counter has a modulus of 8, meaning there are 8 unique output states.

Johnson Counter 0000 1000 1100 1110 8 unique states 1111 0111 0011 0001
Registers 1.53

State Diagram
A State Diagram is used to describe the sequence of output states of a circuit. The state diagram for the previous Johnson counter looks like this:
1000
0000 0001 0011 0111
Registers 1.54

1100 1110 1111

State Recognition
One application of registers is to recognize a specific binary number. Sequences of bits are loaded in series into a register. External detection gates will identify if the value matches a predetermined value:

55
Registers 1.55

Comparison of two values

Values stored in shift registers can be compared by using the following circuit :

What is the output be if both binary inputs are the same? 56

Registers 1.56

Delay Line
A SISO shift register may be used to introduce delay del t in digital signals del t = N x (1/fc) N= number of stages Fc = clock frequency
D Q Q D Q Q
Output

Input

D Q Q

Introduction: Counters
Counters are circuits that cycle through a specified
number of states.

Two types of counters:

synchronous (parallel) counters asynchronous (ripple) counters

Ripple counters allow some flip-flop outputs to be

used as a source of clock for other flip-flops.

Synchronous counters apply the same clock to all

flip-flops.

Introduction: Counters

58

Asynchronous (Ripple) Counters

Asynchronous (Ripple) Counters

Asynchronous counters: the flip-flops do not
change states at exactly the same time as they do not have a common clock pulse. Also known as ripple counters, as the input clock pulse ripples through the counter cumulative delay is a drawback. n n flip-flops a MOD (modulus) 2 counter. (Note: A MOD-x counter cycles through x states.) Output of the last flip-flop (MSB) divides the input clock frequency by the MOD number of the counter, hence a counter is also a frequency divider.
Asynchronous (Ripple) Counters 60

Asynchronous (Ripple) Counters

Example: 2-bit ripple binary counter. Output of one flip-flop is connected to the clock
input of the next more-significant flip-flop.
HIGH J CLK C K FF0 CLK Q0 Q0 Q1 0 0 1 0 0 1 1 1 0 0
61

Q0 Q0

J C K FF1

Q1

Timing diagram 00 01 10 11 00 ...

Asynchronous (Ripple) Counters

Asynchronous (Ripple) Counters

Example: 3-bit ripple binary counter.
HIGH J CLK C K FF0 Q0 Q0 J C K Q1 Q1 J C K FF2 Q2

FF1

CLK Q0 Q1 Q2 0 0 0

1 1 0 0

2 0 1 0

3 1 1 0

4 0 0 1

5 1 0 1

6 0 1 1

7 1 1 1

8 0 0 0 Recycles back to 0

Asynchronous (Ripple) Counters

62

Asynchronous (Ripple) Counters

Propagation delays in an asynchronous (ripple-

clocked) binary counter. If the accumulated delay is greater than the clock pulse, some counter states may be misrepresented!
CLK Q0 Q1 Q2 tPLH (CLK to Q0) 1 2 3 4

tPHL (CLK to Q0) tPLH (Q0 to Q1)

tPHL (CLK to Q0) tPHL (Q0 to Q1) tPLH (Q1 to Q2)

Asynchronous (Ripple) Counters

63

Asynchronous (Ripple) Counters

Example: 4-bit ripple binary counter (negativeedge triggered).
HIGH J CLK C K FF0 CLK 1 Q0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Q0 J C K FF1 Q1 J C K FF2 Q2 J C K FF3 Q3

Q1
Q2 Q3

Asynchronous (Ripple) Counters

64

Asyn. Counters with MOD no. < 2

States may be skipped resulting in a truncated

sequence. Technique: force counter to recycle before going through all of the states in the binary sequence. Example: Given the following circuit, determine the counting sequence (and hence the modulus no.)
C All J, K inputs are 1 (HIGH).
Q CLK Q CLR K Q J

Q CLK CLR

J K

Q CLK Q CLR

J K

B C
Asynchronous Counters with MOD number < 2^n 65

Asyn. Counters with MOD no. < 2

Example (contd):
C All J, K inputs are 1 (HIGH).
Q CLK Q CLR K Q J

Q CLK CLR

J K

Q CLK Q CLR

J K

B C Clock A B C NAND 1 Output 0

Asynchronous Counters with MOD number < 2^n 66

10 11 12

MOD-6 counter produced by clearing (a MOD-8 binary counter) when count of six (110) occurs.

Asyn. Counters with MOD no. < 2

Example (contd): Counting sequence of
circuit (in CBA order).
1 2 3 4 5 6 7 8 9 10 11 12

Clock A 0 0 B 0 C NAND 1 Output 0

1 0 0

0 1 1 1 0 0

0 0 1

1 0 1

0 1 0 0 0 0

Temporary state

111 110 101

000 001 010 011 100

Counter is a MOD-6 counter.

Asynchronous Counters with MOD number < 2^n

67

Asyn. Counters with MOD no. < 2

5 counter? MOD-7 counter? MOD-12 counter?

Exercise: How to construct an asynchronous MOD-

Question: The following is a MOD-? counter?

F
Q Q J K

Q Q

J K

Q Q

J K

Q Q

J K

Q Q

J K

Q Q

J K

CLR

CLR

CLR

CLR

CLR

CLR

C D E F

All J = K = 1.

Asynchronous Counters with MOD number < 2^n

68

Asyn. Counters with MOD no. < 2

Decade counters (or BCD counters) are counters

with 10 states (modulus-10) in their sequence. They are commonly used in daily life (e.g.: utility meters, odometers, etc.). Design an asynchronous decade counter.
(A.C)' HIGH J CLK C K CLR Q D C B A

J C K CLR

J C K CLR

J C K CLR

Asynchronous Counters with MOD number < 2^n

69

Asyn. Counters with MOD no. < 2

HIGH J CLK C K Q

Asynchronous decade/BCD counter (contd).

D
J C K Q

J C K

J C K

(A.C)'

CLR

CLR

CLR

CLR

Clock D C B A NAND output

1
0 1

2
0

3
1

4
0

5
1

6
0

7
1

8
0

9
1

10
0 0 0 0

11

0
0 0

0
0 0

1
0 0

1
0 0

0
1 0

0
1 0

1
1 0

1
1 0

0
0 1

0
0 1

Asynchronous Counters with MOD number < 2^n

70

Asynchronous Down Counters

So far we are dealing with up counters. Down
counters, on the other hand, count downward from a maximum value to zero, and repeat. Example: A 3-bit binary (MOD-23) down counter.
1 J CLK Q

Q0

Q1

Q2

C Q' K 1 J Q Q0

C K Q'

C K Q'

3-bit binary up counter

Q1

Q2

CLK

C Q' K

C K Q'

C K Q'

3-bit binary down counter

Asynchronous Down Counters

71

Asynchronous Down Counters

Example: A 3-bit binary (MOD-8) down counter.
1 J CLK K C Q' K Q0 Q J C Q' K Q1 Q J C Q' Q2 Q

000 001 010 011 101

111
110

100
CLK Q0 Q1 Q2 0 0 0 1 1 1 1 2 0 1 1 3 1 0 1 4 0 0 1 5 1 1 0 6 0 1 0 7 1 0 0 8 0 0 0

Asynchronous Down Counters

Cascading Asynchronous Counters

Larger asynchronous (ripple) counter can be
constructed by cascading smaller ripple counters. Connect last-stage output of one counter to the clock input of next counter so as to achieve highermodulus operation. Example: A modulus-32 ripple counter constructed from a modulus-4 counter and a modulus-8 counter.
Q0 J CLK Q J Q Q1 J Q Q2 J Q Q3 J Q Q4

C Q' K

C K Q'

C Q' K

C K Q'

C K Q'

Modulus-4 counter

Modulus-8 counter
73

Cascading Asynchronous Counters

Cascading Asynchronous Counters

Example: A 6-bit binary counter (counts from
A0 A1 A2 3-bit binary counter
A5 0 0 0 0 0 0 : A4 0 0 0 0 0 0 : A3 0 0 0 0 1 1 : A2 0 0 : 1 0 0 :

0 to 63) constructed from two 3-bit counters.

A3 A4 A5 3-bit binary counter
A1 0 0 : 1 0 0 : A0 0 1 : 1 0 1 :
74

Count pulse

Cascading Asynchronous Counters

Cascading Asynchronous Counters

If counter is a not a binary counter, requires

additional output. Example: A modulus-100 counter using two decade counters.

1
CLK freq

CTENDecade TC counter C Q3 Q2 Q1 Q0

freq/10

CTENDecade TC counter C Q3 Q2 Q 1 Q0

freq/10 0

TC = 1 when counter recycles to 0000

Cascading Asynchronous Counters

75

Synchronous (Parallel) Counters

Synchronous (parallel) counters: the flip-flops are

clocked at the same time by a common clock pulse. We can design these counters using the sequential logic design process. Example: 2-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical J,K inputs).
Present state Next state Flip-flop inputs

00 11

01 10

A1 A0 0 0 0 1 1 0 1 1

A1+ A0+ 0 1 1 0 1 1 0 0

TA1 TA0 0 1 1 1 0 1 1 1

Synchronous (Parallel) Counters

76

Synchronous (Parallel) Counters

Example: 2-bit synchronous binary counter (using T
flip-flops, or JK flip-flops with identical J,K inputs).
Present state Next state Flip-flop inputs

A1 A0 0 0 0 1 1 0 1 1

A1+ A0+ 0 1 1 0 1 1 0 0
1

TA1 TA0 0 1 1 1 0 1 1 1

TA1 = A0 TA0 = 1

A0

A1

C Q' K CLK

C K Q'

Synchronous (Parallel) Counters

77

Synchronous (Parallel) Counters

Example: 3-bit synchronous binary counter (using T
flip-flops, or JK flip-flops with identical J, K inputs).
Present state A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A1
1

A2+ 0 0 0 1 1 1 1 0

Next state A1+ A0+ 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0

1

Flip-flop inputs TA2 TA1 TA0 0 0 1 0 1 1 0 0 1 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 A1

1 1 1 1 1

A1
1 1 1 1

A2 A0

A2

A2

A0

A0

TA2 = A1.A0

TA1 = A0
Synchronous (Parallel) Counters

TA0 = 1
78

Synchronous (Parallel) Counters

Example: 3-bit synchronous binary counter (contd).
TA2 = A1.A0
A2
Q J K J

TA1 = A0 TA0 = 1
A1
Q K J

A0
Q K

CP 1

Synchronous (Parallel) Counters

79

Synchronous (Parallel) Counters

Note that in a binary counter, the nth bit (shown
underlined) is always complemented whenever
01111 10000
or 11111 00000

Hence, Xn is complemented whenever

Xn-1Xn-2 ... X1X0 = 1111.

As a result, if T flip-flops are used, then

TXn = Xn-1 . Xn-2 . ... . X1 . X0

Synchronous (Parallel) Counters

80

Synchronous (Parallel) Counters

Example: 4-bit synchronous binary counter.
TA3 = A2 . A1 . A0 TA2 = A1 . A0 TA1 = A0 TA0 = 1
1
J Q A0 J Q A1 A1.A0 J Q A2

A2.A1.A0
J Q A3

C Q' K CLK

C K Q'

C K Q'

C K Q'

Synchronous (Parallel) Counters

81

Synchronous (Parallel) Counters

Example: Synchronous decade/BCD counter.
Clock pulse Initially 1 2 3 4 5 6 7 8 9 10 (recycle) Q3 0 0 0 0 0 0 0 0 1 1 0 Q2 0 0 0 0 1 1 1 1 0 0 0 Q1 0 0 1 1 0 0 1 1 0 0 0 Q0 0 1 0 1 0 1 0 1 0 1 0

T0 = 1 T1 = Q3'.Q0 T2 = Q1.Q0 T3 = Q2.Q1.Q0 + Q3.Q0

Synchronous (Parallel) Counters

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Synchronous (Parallel) Counters

(contd).
T0 = 1 T1 = Q3'.Q0 T2 = Q1.Q0 T3 = Q2.Q1.Q0 + Q3.Q0
Q0 1 T C CLK Q Q' T C Q Q' Q1 T C Q Q' Q2 T C Q Q'

Example: Synchronous decade/BCD counter

Q3

Synchronous (Parallel) Counters

83

Up/Down Synchronous Counters

Up/down synchronous counter: a
bidirectional counter that is capable of counting either up or down. An input (control) line Up/Down (or simply Up) specifies the direction of counting.
Up/Down = 1 Count upward
Up/Down = 0 Count downward

Up/Down Synchronous Counters

84

Up/Down Synchronous Counters

Example: A 3-bit up/down synchronous
binary counter.
0 1 2 3 4 5 6 7 Clock pulse Up Q2 0 0 0 0 1 1 1 1 Q1 0 0 1 1 0 0 1 1 Q0 0 1 0 1 0 1 0 1 Down

TQ0 = 1 TQ1 = (Q0.Up) + (Q0'.Up' ) TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )

Up/Down Synchronous Counters

Up counter TQ0 = 1 TQ1 = Q0 TQ2 = Q0.Q1

Down counter TQ0 = 1 TQ1 = Q0 TQ2 = Q0.Q1

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Up/Down Synchronous Counters

Example: A 3-bit up/down synchronous
binary counter (contd).
TQ0 = 1 TQ1 = (Q0.Up) + (Q0'.Up' ) TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )
Q0 1 Up T C Q Q' T C Q Q' Q1 T C Q Q' Q2

CLK

Up/Down Synchronous Counters

86

Designing Synchronous Counters

Example: A 3-bit Gray
code counter (using JK flip-flops).
Present state Q2 Q1 Q0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Next state Q1+ 0 1 1 1 0 0 1 0

000
100

001

101
111 110 010

011

Q2+ 0 0 1 0 0 1 1 1

Q0+ 1 1 0 0 0 0 1 1

JQ2 KQ2 0 X 0 X 1 X 0 X X 1 X 0 X 0 X 0

Flip-flop inputs JQ1 KQ1 JQ0 KQ0 0 X 1 X 1 X X 0 X 0 0 X X 0 X 1 0 X 0 X 0 X X 1 X 0 1 X X 1 X 0

87

Designing Synchronous Counters

Designing Synchronous Counters

3-bit Gray code counter: flip-flop inputs.
Q2 Q 1Q 0
00 01 11 10 0 1 X X X 1 X

Q2

Q 1Q 0
00 01 11 10 0 1 X X 1 X X

Q2

Q 1Q 0
00 01 11 10 0 1 X X 1 X X 1

JQ2 = Q1.Q0'

JQ1 = Q2'.Q0

JQ0 = Q2.Q1 + Q2'.Q1' = (Q2 Q1)'

Q2

Q 1Q 0
00 01 11 10 0 X X X X

Q2

Q 1Q 0
00 01 11 10 0 X X

Q2

Q 1Q 0
00 01 11 10 0 X 1 X

1 1

1 X

1 X

KQ2 = Q1'.Q0'

KQ1 = Q2.Q0

KQ0 = Q2.Q1' + Q2'.Q1 = Q 2 Q1

88

Designing Synchronous Counters

Designing Synchronous Counters

3-bit Gray code counter: logic diagram.
JQ2 = Q1.Q0' KQ2 = Q1'.Q0' JQ1 = Q2'.Q0 KQ1 = Q2.Q0 JQ0 = (Q2 Q1)' KQ0 = Q2 Q1

J C

Q0

J C

Q1 Q1'

J C

Q2 Q2'

K Q' Q0' CLK

K Q'

K Q'

Designing Synchronous Counters

89

 Decoding a counter involves determining

Decoding A Counter

which state in the sequence the counter is in. Differentiate between active-HIGH and activeLOW decoding. Active-HIGH decoding: output HIGH if the counter is in the state concerned. Active-LOW decoding: output LOW if the counter is in the state concerned.

Decoding A Counter

90

Decoding A Counter
Example: MOD-8 ripple counter (active-HIGH
decoding).
Clock A' B' C' A' B' C A' B C' A B C
Decoding A Counter

10

HIGH only on count of ABC = 000

HIGH only on count of ABC = 001

HIGH only on count of ABC = 010 HIGH only on count of ABC = 111

. . .

91

Decoding A Counter
Example: To detect that a MOD-8 counter is in
state 0 (000) or state 1 (001).
Clock A' B'
0 1 2 3 4 5 6 7
A' B' C' A' B' C

10

HIGH only on count of ABC = 000 or ABC = 001

Example: To detect that a MOD-8 counter is in the odd

states (states 1, 3, 5 or 7), simply use C.
Clock
C
0 1 2 3 4 5 6 7 8 9 10

HIGH only on count of odd states

Decoding A Counter

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Counters with Parallel Load

Counters could be augmented with parallel load
capability for the following purposes:
To start at a different state To count a different sequence As more sophisticated register with

increment/decrement functionality.

Counters with Parallel Load

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Counters with Parallel Load

Different ways of getting a MOD-6 counter:
A 4 A3 A2 A1 A4 A3 A2 A1 Load I4 I3 I2 I1 Inputs = 0 Count = 1 Clear = 1 CP Clear I4 I3 I2 I1 Inputs have no effect Count = 1 Load = 0 CP

(a) Binary states 0,1,2,3,4,5.

A 4 A3 A2 A1 Carry-out Load I4 I3 I2 I1 1 0 1 0 Count = 1 Clear = 1 CP

(b) Binary states 0,1,2,3,4,5.

A4 A3 A2 A1 Count = 1 Clear = 1 CP

Load I4 I3 I2 I1 0 0 1 1

(c) Binary states 10,11,12,13,14,15.

Counters with Parallel Load

(d) Binary states 3,4,5,6,7,8.

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Counter application: Digital Clock