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Design correct?
Yes
Design Entry (1 of 2)
The desired circuit is specified by: A schematic diagram A hardware description language, such as: Verilog VHDL AHDL
Design Entry (2 of 2)
Synthesis
The entered design is synthesized into a circuit that consists of the logic elements (LEs) provided in the FPGA chip. LE is the smallest unit of logic of Alteras FPGA. Its compact and provides advanced features with efficient logic ultilization. This course doesnt cover the architecture of Alteras FPGA
LE logic element
The placement of the LEs defined in the netlist into the LEs in an actual FPGA chip, also choose routing wires in the chip to make the required connections between specific LEs
Timing Analysis
Analyze the propagation delays along the various paths in the fitted circuit
Timing Simulation
The fitted circuit is tested to verify both its functional correctness and timing
The design circuit is implemented in a physical FPGA chip by programming the configuration switches that configure the LEs and establish the required wiring connections
What is a Project ? - A logic circuit or subcircuit - A project is: + checked for design entry errors + compiled + simulated (functional or timing) + analyzed for timing + used to generate programming file Quartus II works on one project at a time and keeps all information for that project in a single directory (folder).
Quartus II - Summary
module light(x1,x2,f);
input
output assign endmodule
x1,x2;
f; f = (x1&~x2)|(~x1&x2);
Select File > New to get the right figure, then choose Verilog HDL File, and click OK
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Design Entry using Verilog Quartus II Text Editor (6 of 6) We can change the options of Text Editor of Quartus II by the settings in Tools > Options > Text Editor
Compilation (1 of 2)
Verilog code in the design file light.v is processed by the application program called the Compiler. The Compiler :
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Compilation (2 of 2)
Pin Assignment
Purpose: map the I/O signals of your design to the physical pins of selected FPGA. Pin assignments are made by: Assignment Editor (manual), or Import a pin assignment from a special file format comma separated value (CSV) format. Note: All relevant pin assignments for the DE2 board are given in the file called DE2_pin_assignments.csv in the CD-ROM or on the Alteras DE2 web pages.
We will connect the output f to the green light-emitting diode labeled LEDG0 (PIN_AE22)
entry <<new>> which is highlighted in blue in the column labeled To. The drop-down menu appear. Click on x1 3. Double click on the box into the column labeled Location. The drop-down menu appear. Scroll down and select PIN_N25
Chossing Assignments > Import Assignments Type (or browse to find) the full path to the directory that hold DE2_pin_assignments.csv
Recompile
Simulating
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10. Enter 200ns in this dialog box
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13. Setting displays the entire simulation range of 0 to 200ns in the waveform window
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16. This utility has a filter used to indicated what type of nodes are to be found
15. To include the input and output nodes of the circuit to be simulated
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17. Set the filter to Pins:all if we are interested in input and output pins
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31.We setted x1 to 1 from 100ns to 200ns. For setting x2 to 1from 50 to 100ns and also 150 to 200ns, you do as follows:
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32. Press the mouse at 50ns and drag it to 100ns.Then, choose the logic 1 in the tool bar
33. Press the mouse at 150ns and drag it to 200ns.Then, choose the logic 1 in the tool bar
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Check the value of f as the output of EX-OR with two inputs x1 and x2: f=0 iff x1 = x2
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There is a delay of about 6ns in producing a change in the signal f from the time when the input signal x1 or x2 change the their values. The delay is due to the propagation delay in the logic element and the wires in the FPGA device.
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58. If not ready choose by default, select JTAG in the Mode box
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62 61. If the USB-Blaster is not choosen by defaut, select USB-Blaster in this window
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AS = Active Serial If the FPGA is configured in AS mode, the configuration data has to be loaded into the configuration device, which is identified by the name EPCS16. Then, this data is loaded into the FPGA upon power up or reconfiguration. In this mode, you must flip the RUN/PROG switch of DE2 board into the PROG position
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78. If not ready choose by default, select Active Serial Programming in the Mode box
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79. If you are changing the Mode from the previously JTAG mode, this box ask if you want to clear all devices
80. If the configuration file is not already listed in the window, press Add File
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85. Press Start. Note to flip the RUN/PROG switch on the DE2 board to the PROG position
Some references
"Altera's Quartus II software is such a superior development environment that I am quickly forgetting about any other PLD (programmable logic device) design tool."
"Quartus II software is superior compared to other programmable logic tool offerings, which allows us to focus our time on meeting customer needs, rather than laboring over tool usage.