Академический Документы
Профессиональный Документы
Культура Документы
=
( )
F SB F
V | | 2 2 + +
ox
ox
ox
B
F GC
T
C
Q
C
Q
V
u = | 2
CMOS Digital Integrated Circuits 13
Threshold Voltage Components (Cont.)
The final expression for V
T0
and V
T
are
and
The threshold voltage depends on the source-to-bulk voltage which
is clearly separated out. The component is referred to as body
effect. If the source to body voltage V
SB
is non-zero, the corrective
term must be applied to V
T0
.
C
N
q
ox
S
A
i
c
2
=
( )
F SB F
T T
V
V V
| | 2 2
0
+ + =
ox
ox
ox
B
F GC
T
C
Q
C
Q
V
u =
0
0
2|
CMOS Digital Integrated Circuits 14
Threshold Voltage Components (Cont.)
Those parameters in the V
T
equation are signed. The
following table gives their signs for nMOS and pMOS
transistor.
For real designs, the threshold voltage, due to variation in
oxide thickness, impurity concentrations, etc., V
T0
and
should be measured from the actual process.
Parameter nMOS pMOS
|
F
+
Q
B
, Q
B0
+
+
V
SB
+
CMOS Digital Integrated Circuits 15
Threshold Voltage
Adjustment by Ion Implant
Depletion mode nMOS
A channel implanted with donors can be present for V
GS
<0.
For this nMOS V
T
<0. Its symbols are as follows:
G
D
B
S
G
D
S
D
S
G G
D
S
CMOS Digital Integrated Circuits 16
MOSFET Modes of Operation
Cutoff
Assume n-channel MOSFET and V
SB
=0
Cutoff Mode: 0V
GS
<V
T0
The channel region is depleted and no current can flow
gate
drain source
I
DS
=0
V
GS
< V
T0
CMOS Digital Integrated Circuits 17
MOSFET Modes of Operation
Linear
Linear (Active, Triode) Mode: V
GS
V
T0,
0V
DS
V
D(SAT)
Inversion has occurred; a channel has formed
For V
DS
>0, a current proportional to V
DS
flows from source to
drain
Behaves like a voltage-controlled resistance
gate
drain source
current
I
DS
V
DS
< V
GS
V
T0
CMOS Digital Integrated Circuits 18
MOSFET Modes of Operation
Pinch-Off
Pinch-Off Point (Edge of Saturation) : V
GS
V
T0,
V
DS
=V
D(SAT)
Channel just reaches the drain
Channel is reduced to zero inversion charge at the drain
Drifting of electrons through the depletion region between the channel
and drain has begun
gate
drain source
current
I
DS
V
DS
= V
GS
V
T0
CMOS Digital Integrated Circuits 19
MOSFET Modes of Operation
Saturation
Saturation Mode: V
GS
V
T0,
V
DS
V
D(SAT)
Channel ends before reaching the drain
Electrons drift, usually reaching the drift velocity limit, across the
depletion region to the drain
Drift due to high E-field produced by the potential V
DS
-V
D(SAT)
between the drain and the end of the channel
gate
drain source
I
DS
V
DS
> V
GS
V
T0
CMOS Digital Integrated Circuits 20
MOSFET I-V Characteristics
Gradual Channel Approximation
Preliminaries
Gradual channel approximation will reduce the analysis to a one-
dimensional current flow problem.
Assumption
V
SB
=0
V
T0
is constant along the entire channel
E
y
dominates E
x
Only need to consider the current-flow in
the y-dimension
Cutoff Mode: 0V
GS
<V
T0
I
DS(cutoff)
=0
CMOS Digital Integrated Circuits 21
Gradual Channel Approximation
Linear Mode
Linear Mode: V
GS
V
T0,
0V
DS
V
D(SAT)
=> V
DS
V
GS
<V
T0
The channel reaches to the drain.
V
c
(y): Channel voltage with respect to the source at position y
Boundary Conditions: V
c
(y=0)=V
s
=0; V
c
(y=L)=V
DS
Drain
n+
Source
n+
Substrate (p-Si)
(p+)
(p+)
Oxide
x
Channel
Depletion region
V
B
=0
V
S
=0
V
GS
>V
T0
V
DS
<V
DSAT
y=0
y
y=L
CMOS Digital Integrated Circuits 22
Gradual Channel Approximation
Linear Mode (Cont.)
Q
I
(y): the mobile electron charge density in the surface inversion layer.
Q
I
(y)=-C
ox
[V
GS
-V
C
(y)-V
T0
]
The differential resistance (dR) of the channels can represented in terms
of the mobile electron charge (Q
I
(y)) in the surface inversion layer, and
the electron surface mobility
n
(about of the bulk electron mobility)
dy
Source end
Drain end
x
l
Channel
CMOS Digital Integrated Circuits 23
Gradual Channel Approximation
Linear Mode (Cont.)
The differential resistance (dR) of the channels can represented in
terms of the mobile electron charge (Q
I
(y)) in the surface
inversion layer, and the electron surface mobility
n
(about of
the bulk electron mobility)
) ( ) ( y
I n
y
d A
n
n n
Q W
dy
Wx N
q
dy
A
dy
dR
o
= = =
dy
Source end
Drain end
x
d
Channel
dy
Q W
I
dR I dV
y
I n
D
D c
) (
= =
CMOS Digital Integrated Circuits 24
Gradual Channel Approximation
Linear Mode (Cont.)
Integrating the Ohms Law equality between the differential voltage
in the channel and the differential resistance times the drain current,
dV
Q W dy
I
c
DS
y
V
I n
L
D
) (
0 0
} }
=
dy
Source end
Drain end
x
d
Channel
( )
dV V V V C
W
L I
c
V
T c GS ox
n
D
DS
}
=
0
0
k k = = '
CMOS Digital Integrated Circuits 26
Gradual Channel Approximation
Pinch-Off, Saturation
Pinch-Off Point (Edge of Saturation) : V
GS
V
T0,
V
DS
=V
D(SAT)
Channel just reaches the drain but is reduced to zero inversion charge
at the drain
Electrons drift through the depletion region between the channel and
drain
Saturation Mode: V
GS
V
T0,
V
DS
V
GS
- V
T0
In pinch-off voltage from the channel end to the source is V
D(SAT)
=V
GS
- V
T0.
Substituting this for V
DS
in the equation for I
D
gives:
2
0 ) (
) (
2
V V
L
W
C
I
T GS
ox
n
SAT D
=
CMOS Digital Integrated Circuits 27
MOSFET I-V Characteristics
I-V Plots, Channel Length Modulation
Saturation equation yields curves independent of V
DS
. Not sure! So
we consider the effect of channel length modulation.
Quadratic
Relationship
0 0.5 1 1.5 2 2.5
0
1
2
3
4
5
6
x 10
-4
V
DS
(V)
I
D
(
A
)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive Saturation
V
DS
= V
GS
- V
T
CMOS Digital Integrated Circuits 28
MOSFET I-V Characteristics
Channel Length Modulation
Channel Length Modulation
With pinch-off the channel at the point y such that V
c
(y)=V
GS
- V
T0
, The
effective channel length is equal to L = L L
L is the length of channel segment over which Q
I
=0.
Place L in the I
D(SAT)
equation:
2
0 ) (
) (
2
V V
L
W
C
I
T GS
ox
n
SAT D
'
=
L
Drain
n+
Source
n+
Substrate (p-Si)
(p+)
(p+)
Oxide
0
y
L
L
Channel
Pinch-off point (Q
I
=0)
Depletion region
V
B
=0
V
S
=0
V
GS
>V
T0
V
DS
>V
DSAT
CMOS Digital Integrated Circuits 29
MOSFET I-V Characteristics
Channel Length Modulation
L increases with an increase in V
DS
. We can use
: channel length modulation coefficient
I
D(SAT)
can be rewritten as
The above form produces a discontinuity of current at V
DS
=V
GS
-V
T0
.
We can include the term in I
D(lin)
with little error since is typically
less than 0.1. We will usually ignore in manual calculations.
( )
V
L
V
L
L
L
L
L
L L
L L L L
DS
DS
+ =
= 1
1
1
1 1
1
1 1 1 1 1
'
1
) 1 ( ) (
2
2
0 ) ( V V V
L
W
C
I
DS T GS
ox
n
SAT D
+ =
CMOS Digital Integrated Circuits 30
MOSFET I-V Characteristics
Substrate Bias Effect
So far, V
SB
=0 and thus V
T0
used in the equations.
Clearly not always true must consider body effect
Two MOSFETs in series:
V
SB(M1)
= V
DS(M2)
0. Thus, V
T0
in the M1 equation is replaced by
V
T
= V
T(V
SB
)
as developed in the threshold voltage section.
D
S
G
D
G
M1
M2
V
SB
S
CMOS Digital Integrated Circuits 31
MOSFET I-V Characteristics
Substrate Bias Effect (Cont.)
The general form of I
D
can be written as
I
D
= f (V
GS
,V
DS
,V
SB
)
which due to the body effect term is non-linear and more difficult to
handle in manual calculations
CMOS Digital Integrated Circuits 32
MOSFET I-V Characteristics
Summary of Analytical Equations
The voltage directions and relationships for the three modes of
pMOS are in contrast to those of nMOS.
nMOS
Mode I
D
Voltage Range
Cut-off 0 V
GS
<V
T
Linear (
n
C
ox
/2)(W/L)[2(V
GS
-V
T
)V
DS
-V
DS
2
] V
GS
>V
T
V
DS
< V
GS
-V
T
Saturation (
n
C
ox
/2)(W/L)(V
GS
-V
T
)
2
(1+V
DS
) V
GS
> V
T
V
DS
> V
GS
-V
T
pMOS
Cut-off 0 V
GS
>V
T
Linear (
n
C
ox
/2)(W/L)[2(V
GS
-V
T
)V
DS
-V
DS
2
] V
GS
s
V
T
V
DS
> V
GS
-V
T
Saturation (
n
C
ox
/2)(W/L)(V
GS
-V
T
)
2
(1+V
DS
) V
GS
s V
T
V
DS
sV
GS
-V
T
G
D
B
S
V
DS
V
SB
V
GS
I
D
G
S
B
D
V
DS
V
SB
V
GS
I
D
CMOS Digital Integrated Circuits 33
More Parameter Extraction
Need numerical values for parameters in V
T
and I
D
equations
Parameters can be derived from the measured I-V characteristics
for a given MOSFET process.
To illustrate, seeking Level 1 Spice model parameters V
T0
,
n
(
n
),
, and
To obtain V
T0
,
n
(
n
), and , we plot (I
D
)
1/2
vs V
DS
= V
GS
with V
SB
set to zero and one positive value. MOSFET is in saturation mode
(ignoring channel length modulation):
Note that this (ideally!) gives a linear relationship that will allow
us to determine
n
and V
TO
.
The slope of the lines is
The intercept of the V
SB
= 0 line with the V
GS
axis is V
T0
) (
2
0
V V I
T GS
n
D
=
k
2 /
kn
CMOS Digital Integrated Circuits 34
More Parameter Extraction (Cont.)
Using the intercept of the line for V
SB
nonzero, the body effect
coefficient can be found
|
F
can be obtained from the substrate acceptor density N
A
and
other known physical constants
( )
| |
F
SB
F
T SB T
V
V V V
2 2
0
+
=
I
D
V
DS
= V
GS
V
SB
V
T1
V
T0
I
D
V
GS
V
SB
= 0
V
SB
> 0
Slope =
2 /
n
k
CMOS Digital Integrated Circuits 35
More Parameter Extraction (Cont.)
The I-V curve for V
GS
= V
T0
+1 can be used to obtain .
I
D
(sat) =
n
/2(V
GS
-V
T0
)
2
(1+ V
DS
)=
n
/2(1+ V
DS
)
Therefore
=2S/
n
where S is the slope of this curve in the saturation region.
I
D
V
DS
V
GS
V
DS2
V
DS1
V
DS
I
D1
V
GS
= V
T0
+ 1
I
D2
I
D
CMOS Digital Integrated Circuits 36
More Parameter Extraction (Cont.)
The Level 1 model is valid only for long devices and is obsolete
for most of todays technologies for detail simulation.
Parameter extraction for more advanced models such as Level 3 or
4 is usually performed by an automatic parameter extraction
system that optimizes the combined parameter values for a best
non-linear fit to the I-V curves.
Due to this optimization, derivation of Level 1 model by simply
deleting selected parameters from a Level 3 model is invalided.
Instead, use the Level 3 model to produce I-V curves and linear
curve fitting to extract Level 1 parameters.
CMOS Digital Integrated Circuits 37
Summary
Basic MOSFET operation
Components of the threshold voltage
Threshold voltage and body effect
Drain currents
MOSFET static parameter extraction from I-V plots
All of the above for both nMOS and pMOS.