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Design Methodology

Semi Custom ASIC FPGA

VLSI Design Methodology


Design Rules

Silicon Foundry

Simulation Models and parameters


Mask Layouts Integrated circuits (IC)

IC Design Team

Process Information

CAD Tool Provider

Software Tools

Relationship between a silicon foundry, an IC design team and a CAD tool provider

Top Down (algorithm)

Bottom Up (physical)

Application Specific Integrated Circuits (ASICs)


IC

Standard IC

ASSPs

ASIC

Programmable IC

Semi Custom IC

Custom IC

FPGA

Gate Array

Linear Array

Standard Cells

Full Custom IC

ASSPs : Application Specific Standard Products

ASIC Design Methodologies


ASIC Design Methodology

Full-custom design
This approach is extremely slow, expensive It is only used to design very high performance systems

Standard-cell based design


This approach is reasonable fast, less expensive Most ASICs are currently designed using this method

Gate-array based design


This approach is fast and less expensive ASIC performance are relatively slow

FPGA based design


The design process is very fast and cost effective ASIC performance are slow

ASIC-Benefit
Improve performance Reduce power consumption Mix Analog and Digital Designs Design optimization through IC manufacturing process Development Tools support HDL and Schematic design approach

ASIC-Drawbacks
Inflexible design Deployed systems can not be upgraded Mistakes in product development are costly Updates requires a redesign Complex and expensive development tools

Session Outline (FPGA)

Technology/price breakthrough in FPGA devices


Why should Windows hardware developers care? Survey of new technologies/vendors Business comparison of FPGA with alternative solutions Advantages/requirements for FPGA development Pleora iPort Pinnacle Studio Movie Box Deluxe

Case Studies

Summary/Conclusions
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Technology Breakthrough Impacts Windows-Compatible Hardware Market

Field Programmable Gate Arrays (FPGAs) break through price/capability barriers

1 million gates drop from $200+ to <$20 90nm will offer another >2X improvement 32 bit RISC processors for free

Embedded soft 32-bit processors debut allowing complete Systemon-Chip designs Previously relegated to high-margin/low-volume applications

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Why Should We Care?


Cost-effective FPGAs Enable New WindowsCompatible Products Greater product differentiation Functionality and performance never available at this price point Shorter development cycles = faster time to market Improved product flexibility = longer market life Reduced part inventory More product variants

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New Low-Cost Technologies

FPGA Families

Altera: Cyclone Xilinx: Spartan 3 QuickLogic: QuickMIPS, Eclipse II Actel: ProASIC Plus

Embedded Processors

Altera: Nios Xilinx: MicroBlaze QuickLogic: MIPS Actel: 8051

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Three Choices For WindowsCompatible Hardware Development


1.

Develop conservative products based on standard chipsets

Little differentiation Minimal margin Straight to commodity

Develop an ASIC 3. Use new FPGA technologies Lets compare options 2 and 3
2.
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ASIC Versus FPGA Comparison


Tooling cost Non-recurring engineering costs (NRE) Time to market Product risk Product flexibility Inventory simplification

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ASIC Versus FPGA Tools

ASIC Requirements

Average seat of EDA tools $200K/engineer

HDL Simulation, Synthesis, Timing analysis,

Test insertion,

Place-and route, Formal verification, Floorplanning, DRC

Usually involves multiple EDA vendors Average seat $2K-$3K/yr


FPGA Requirements

Simulation, Synthesis, Place-and-route

Adequate tools provided by FPGA vendors

Value-added tools from EDA vendors ~$20-30K


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Non-Recurring Engineering (NRE)

ASIC Designs

NRE for ASIC Designs ~$500K/run for .13 Each subsequent re-spin costs another NRE For new 90nm technology NRE >$1M High-risk methodology requiring massive volume to recoup costs No NRE charges Some cost-reduction available by ASIC conversion with minimal (<$100K) NRE

FPGA Designs

Cost of FPGA device is offset by NRE in all but the highest volume applications

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Time To Market

ASIC Designs

Typical design cycle 12-18 months, minimum 9 months Additional re-spins add 8-10 weeks each Typical design cycle 4 months Re-spins not an issue

FPGA Designs

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Extremely Fast Time-To-Prototype

Software-based prototype in days

System assembly on FPGA in minutes with processor, memory, bus, interfaces, peripherals C/C++ based application (with RTOS if needed) running in minutes using actual hardware Performance-critical routines easily migrated to hardware implementations Software development in parallel with working hardware Embedded virtual instrumentation offers in-circuit debugging Allows evolutionary design style

Iterative development/refinement flow


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Benefits Of FPGA-Based Design

Improved product flexibility

Changes hardware/software up to (and even after) deployment Inventoried parts can be re-deployed in multiple applications More product variants on single platform Upgrade/enhance in the field Single part for multiple variations and versions of product
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Reduce inventory

Whats Needed For FPGA-Based Product Development?


Complete toolsets provided by FPGA vendors Robust libraries of pre-tested IP components

Processor cores (8,16,32 bit configurable) Peripherals (USB, PCI, I/O, DSP, ethernet, Memory)

Ready-to-use development prototyping boards for a variety of application types Development environments are PC/Windowsbased, no UNIX workstations required

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Case Study: Pleora iPort (~USD500)


High-speed video-over-ethernet peripheral with Altera Cyclone FPGA ~10X price/performance improvement over frame-grabber solutions

Gigabit ethernet versus expensive video cabling Multiple video sources to single PC, or many-to-many Longer reach

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Case Study: Pleora iPort

FPGA-based frame grabber


low-cost, high-speed processing standardized (Ethernet) interfaces

Low cost-per-gate at high performance Flexible memory architecture for buffering Drop-in PCI core for interface with Intel Network I/F

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FPGA Benefits To Pleora

Reduced system cost

Sub-$20 FPGA is 20% of product cost

Dramatically shorter design cycle Multiple product variants with single board

Inventory one part and deliver variations based on product mix

Enabler ASIC-based solution not an option at target volumes

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Pinnacle Studio Movie Box Deluxe (~USD 500)


Without the FPGA option, we probably wouldnt have pursued the project
-

Bernd Riemann, Director Hardware Engineering Pinnacle Systems GmbH

Uses Altera Cyclone FPGA for translation between video/audio I/O Development time 6 mos. with 2 engineers ASIC solution would have added 1 year to development FPGA ~20% of total BOM cost Using FPGA in more and more projects
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Pinnacle Studio Movie Box Deluxe


Remarkable leverage of FPGA reprogrammability 3 FPGAs in 1


Device hardware reconfigures itself based on operating mode Embedded memory sufficient for buffering no external I/O required

Changes made right up to (and after) shipment Hardware design loaded at runtime from Windows drivers

Device shipped with no configuration on board User updates possible by downloading new drivers/patches Separate versions possible for NTSC, PAL, etc. Follow-on improvements could be added in future versions Business immunity from hardware design errors (and marketing errors as well)
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Feature set could be modified with no hardware changes


What Applications Benefit From FPGA?

Windows-compatible applications that challenge performance barriers High computational load:


Digital Signal Processing (DSP) Video Digital TV Speech recognition Embedded soft-cores offer unprecedented capability
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High embedded software content

What Does The Future Hold?


Tomorrows Systems Designer is todays Software Engineer Example: Nallatech, Ltd. of Scotland

Prototyped entire system in C on embedded Xilinx MicroBlaze SW engineer ran project Performance-critical modules moved into hardware (FPGA fabric)

New tools rolling out for C-based HW compilation Windows-compatible hardware becomes an extension of SW applications development
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Summary

FPGAs offer significant benefits to PC-based hardware development projects


Reduced/more predictable development schedules Earlier prototypes Lower development cost More flexible, upgradeable products with longer market life Greater capability/performance at lower price point Reduced BOM, more flexible inventory Reduced product risk

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Community Resources

Community Sites

http://www.microsoft.com/communities/default.mspx http://communities2.microsoft.com/communities/newsgroups/enus/default.aspx http://www.microsoft.com/communities/chats/default.mspx http://www.microsoft.com/seminar/events/webcasts/default.mspx http://www.microsoft.com/communities/usergroups/default.mspx http://www.microsoft.com/communities/related/default.mspx


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List of Newsgroups

Attend a free chat or webcast


Locate a local user group(s)

Non-Microsoft Community Sites