INDUSTRIAL TRAINING

[AT401] Session of December 2011

Present by Chong Wei Ting (18DTK10F1036) SPANSION (Penang) Sdn. Bhd.

Phase II Free Industrial Zone, 11900, Bayan Lepas, Penang.

Course :Diploma in Electronic Engineering(Computer)

Profile Of Company
a) Companys name Spansion Sdn Bhd (Penang)
b) Products Flash Memory, Semiconductor Chip

c) Founded 1993
d) Headquarter Sunnyvale, California, US

e) Manufacturers Austin(US), Bangkok and Penang

f) Global Employees <3400 (around 300 for

Penang branch)

Snapshot Of My Team Organization

FMO Engineering Department Wafer Sort & Operation QE Department

Process engineering develop

IQC/
calibration lab

Teoh LB
Senior manager

Thiyagarajan Senior manager

Tan Gin Ghee Member of technical staff

Namas Karupanan Quality engineer

Chong Wei Ting Industrial Trainee

My Training Activities
1. Main project: TSV Benchmarking Study Project.

Follow up Mr. Tan Gin Ghee

Reformatting subcon control plan Follow up Mr. Tan Gin Ghee (FMO process develop) Assembly process flow study Clean room particle count control Equipment calibration. ESD monitoring Follow up Mr. Namas (IQC & Preventative Maintenances calibration lab) Machine buy-off Dimensional check Measurement system analysis study

2. Extra Training:

THROUGH SILICON VIA BENCHMARKING STUDY

Done by Chong Wei Ting that assigned by Mr. Tan Gin Ghee

What is TSV?
Through-Silicon Via: A via that goes through the silicon substrate by
vertical connection.
Via

Silicon wafer

Evolutions Of Interconnection Technologies

1st generation 2nd generation 3rd generation

NEW Wire bonding Flip chip TSV

Confidential

Why We Need TSV Package????

Connections is shorter.

High speed signal propagation & processing.

Lower power consumption.

Reduce noises

THREE Typical TSV Process Technologies

Via first

Via middle

Via last

Typical TSV Processes Scheme : Via First

Via
Via Forming

Wafer

CMOS
FEOL

Wiring Layer
BEOL

10

Typical TSV Processes Scheme: Via Middle

CMOS
FEOL

Wafer Via

Via Forming

Wiring layer
BEOL

11

Typical TSV Processes Scheme: Via Last

CMOS
FEOL

Wafer

Wiring layer
BEOL

Via
Via Forming

12

BOSCH Process

(Patented process developed in 1994)

1. Use alternating steps between etching and passivation processes.

Source: Oxford instruments

Confidential

13

BOSCH Process Flow (Etching Step)

1. Etch the silicon wafer in one direction.
SF
Mask Mask

Typical ~0.1m

Confidential

14

BOSCH Process Flow (Passivation Step)

2. Deposit the polymer in the surface of silicon and side wall of the Via.
CF

Confidential

15

BOSCH Process Flow (Alternative Step)

3. Etch the polymer and silicon wafer in one direction.

Mask

SF

Mask

Confidential

16

Conclusion, Suggestions & Comments

Conclusion
Can help trainee sense real working world. Improved the interchange of employees. Produced trainee have selfconfidence. Time management capability. Gain experience and seeking valuable knowledge. Technical work handling.

Suggestion & Comments

Provides EHS training. Fixes some critical courses for trainee. Fixes some line tour for trainee. Allowing trainee to request for accommodation

Selamat Berpuasa