Programmable Logic Devices

Tulika Mitra tulika@comp.nus.edu.sg

Copyright 2001 Tulika Mitra

Embedded Systems Technology

Programmable Processors Application Specific Processor (ASIP) Single purpose hardware

Embedded System Technology

Differ in their customization for the problem at hand

total = 0 for i = 1 to N loop total += M[i] end loop

Desired functionality

General-purpose processor
Vahid & Givargis

Application-specific processor

Single-purpose hardware
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General-purpose processors

Programmable device used in a variety of applications

Controller Control logic and State register

Datapath Register file

Also known as microprocessor

Features

Program memory General datapath with large register file and general ALU Low time-to-market and NRE costs High flexibility

IR

PC

General ALU

User benefits

Program memory
Assembly code for:

Data memory

Example: Pentium, ARM,

total = 0 for i =1 to

Vahid & Givargis

NRE and unit cost metrics

Unit cost

the monetary cost of manufacturing each copy of the system, excluding NRE cost The one-time monetary cost of designing the system

NRE cost (Non-Recurring Engineering cost)

total cost = NRE cost + unit cost * # of units per-product cost = total cost / # of units
= (NRE cost / # of units) + unit cost

Vahid & Givargis

Application-specific processors

Programmable processor optimized for a particular class of applications Controller having common characteristics Control logic and Features State register

Datapath Registers

Program memory Optimized datapath Special functional units Some flexibility, good performance, size and power

Custom ALU IR PC Data memory

Benefits

Program memory
Assembly code for: total = 0 for i =1 to

Example: DSP, Media Processor

Vahid & Givargis

Single-purpose hardware

Digital circuit designed to execute exactly one program

coprocessor, accelerator Contains components needed to execute a single program No program memory Fast Low power Small size

Controller Control logic State register

Datapath index

Features

total
+

Benefits

Data memory

Vahid & Givargis

IC technology

Three types of IC technologies

Full-custom/VLSI Semi-custom ASIC (gate array and standard cell) PLD (Programmable Logic Device)

Vahid & Givargis

Full-custom/VLSI

All layers are optimized for an embedded systems particular digital implementation

Placing transistors Sizing transistors Routing wires Excellent performance, small size, low power High NRE cost (e.g., $300k), long time-to-market

Benefits

Drawbacks

Vahid & Givargis

Semi-custom

Lower layers are fully or partially built

Designers are left with routing of wires and maybe placing some blocks

Benefits

Good performance, good size, less NRE cost than a full-custom implementation (perhaps $10k to $100k)
Still require weeks to months to develop

Drawbacks

Vahid & Givargis

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PLD (Programmable Logic Device)

All layers already exist

Designers can purchase an IC Connections on the IC are either created or destroyed to implement desired functionality Field-Programmable Gate Array (FPGA) very popular
Low NRE costs, almost instant IC availability Bigger, expensive (perhaps $30 per unit), power hungry, slower
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Benefits

Drawbacks

Vahid & Givargis

Comparison
Technology Performance/ Cost Time until running Time to high performance Time to change code functionality

Speed

FPGA ASIP/ DSP Generic

Medium High

Medium Long

Long Long Not Attainable

Medium Long Very Short

Low-Medium Very Short

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Flexibility

ASIC

Very High

Very Long Very Long

Impossible

Roadmap
PROM PLA PAL CPLD FPGA

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Reading

Digital Logic Circuit Analysis and Design by

Nelson, Nagle, Carrol, and Irwin : Chapter 5.3, 5.4, 5.5, 11.2

Architectures of FPGAs and CPLDs: A Tutorial

by Stephen Brown and Jonathan Rose [ Available on the web: check out the link from lectures page]

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PLD Definition

Programmable Logic Device (PLD):

An integrated circuit chip that can be configured by end use to implement different digital hardware Also known as Field Programmable Logic Device (FPLD)

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PLD Advantages

Nonrecurring engineering cost PLD

Short design time Less expensive at low volume

ASIC

Volume

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PLD Categorization
PLD
SPLD
Simple PLD

HCPLD
High Capacity PLD

PLA

PAL
Programmable Array Logic

CPLD
Complex PLD

FPGA
Field Programmable Gate Array
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Programmable ROM (PROM)

N input

xM ROM

M output

Address: N bits; Output word: M bits ROM contains 2

N

words of M bits each

The input bits decide the particular word that becomes available on output lines

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Logic Diagram of 8x3 PROM

Sum of minterms
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Combinational Circuit Implementation using PROM

I0 I1 I2 F0 F1 F2
0 0 0 0 0 1 0 0 1 0 1 0

0 0 1 1 1 1

1 1 0 0 1 1

0 1 0 1 0 1

0 1 0 0 1 0

1 0 1 0 0 1

1 0 0 1 0 0

F0

F1

F2
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PROM Types

Programmable PROM

Break links through current pulses Write once, Read multiple times Program with ultraviolet light Write multiple times, Read multiple times

Erasable PROM (EPROM)

Electrically Erasable PROM (EEPROM)/ Flash Memory

Program with electrical signal Write multiple times, Read multiple times
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PROM: Advantages and Disadvantages

Widely used to implement functions with large number of inputs and outputs Design of control units (Micro-programmed control units) For combinational circuits with lots of dont care terms, PROM is a wastage of logic resources

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Programmable Logic Array

n x k links

k AND gates
n inputs n x k links

m OR gates k X m links m outputs

Programmable AND array + programmable OR array n x k x m PLA has 2n x k + k x m links Sum of products
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PLA 4 X 6 X 2

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Logic Implementation with PLA

Finite number of AND gates => simplify function to minimum number of product terms Number of literals in a product term is not important since we have all the input variables Sharing of product terms between outputs => multiple-output minimization

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Design with PLA

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Programmable Array Logic (PAL)

Programmable AND array Fixed OR array

Each output line permanently connected to a specific set of product terms

Number of switching functions that can be implemented with PAL are more limited than PROM and PLA

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PAL Logic Diagram

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PAL Implications

Number of product terms per output > number of product terms in each sum-ofproduct expression No sharing of product terms between outputs

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Design with PAL

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CPLD

I/O Logic Block

Programmable Interconnect

Logic Block

Logic Block I/O Logic Block

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CPLD Logic Block

Simple PLD

Inputs Product-term array Product term allocation function Macro-cells (registers)

Logic blocks executes sum-of-product expressions and stores the results in micro-cell registers Programmable interconnects route signals to and from logic blocks

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Major CPLD Resources

Number of macro-cells per logic block Number of inputs from programmable interconnect to logic block Number of product terms in logic block

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Structure of FPGA (Xilinx)

Logic Block

I/O Block

Interconnect

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Configurable Logic Block CLB

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Logic Function

Implemented as look-up table (LUT) K K-input LUT corresponds to 2 x 1 bit memory K-input LUT can implement any k-input 1output logic function

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Configuring FPGA

Configure CLB and IOB Configure interconnect Interconnect technology

SRAM Anti-fuse (program once) EPROM / EEPROM

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Programming Technology
Name EPROM Re-programmable yes (out of circuit) Volatile no

EEPROM
SRAM Antifuse

yes (in circuit)

yes (in circuit) no

no
yes no

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FPGA Applications

Glue Logic (replace SSI and MSI parts) Rapid turnaround Prototype design Emulation Custom computing Dynamic reconfiguration

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PLD Logic Capacity

SPLD: about 200 gates CPLD

Altera FLEX (250K logic gates) Xilinx XC9500 Xilinx Vertex-E ( 3 million logic gates) Xilinx Spartan (10K logic gates) Altera

FPGA

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FPGA Design Flow

Design Entry

Design Implementation

Design Verification

FPGA Configuration

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Design Entry (DK1 in our case)

Schematic Compile

HDL

Logic Equations Minimize Reduced Logic Equations (Netlist)

Test vectors

Simulation
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Design Implementation

Input: Netlist Output: bitstream Map the design onto FPGA resources

Break up the circuit so that each block has maximum n inputs NP-hard problem However, optimal solution is not required

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Design Implementation (Cont.)

Place: assigns logic blocks created during mapping process to specific location on FPGA

Goal: minimize length of wires Again NP-hard

Route: routes interconnect paths between logic blocks

NP-hard

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Design Implementation Techniques

Simulated annealing Genetic algorithm Mincut method Heuristic method

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Design Verification & FPGA Configuration

Functional Simulation Timing Simulation Download bitstream into FPGA

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