Computer Programming TA C162

Topics to be covered…
•Phases of Instruction processing
•Instruction Set Architecture (ISA) of LC-3 Computer
•Operate Instruction
• AND
• ADD
• NOT

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 Computer Programming TA C162

Recall LC-3 ADD Instruction

Recall LC-3 LDR Instruction

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Instruction Processing: FETCH

Load next instruction from memory into
F
Instruction Register (IR).
• Copy contents of PC into MAR. D
• Send “read” signal to memory.
• Copy contents of MDR into IR. EA

Then increment PC, so that it points to the OP

next instruction in sequence.

EX
• PC becomes PC+1.

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Instruction Processing: DECODE

•First identify the opcode.
F
• In LC-3, this is always the first four bits of
instruction.
D
• A 4-to-16 decoder asserts a control line
corresponding to the desired opcode.
EA
•Depending on opcode, identify other operands from
the remaining bits. OP
• Example:
For LDR, last six bits is offset EX
For ADD, last three bits is source operand #2
S

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Instruction Processing: EVALUATE ADDRESS

F
For instructions that require memory access
to get the operands; compute address used D
for access.
EA

Example:
OP
• Add offset to base register (as in LDR)
EX

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Instruction Processing: FETCH OPERANDS

Obtain source operands needed to perform
F
the operation.
D
Examples:
• Load data from memory (LDR) EA
• Read data from register file (ADD)
OP

EX

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Instruction Processing: EXECUTE

Perform the operation, using the source
F
operands.
D
Examples:
• Send operands to ALU and assert ADD signal EA
• Do nothing (e.g., for loads and stores)
OP

EX

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Instruction Processing: STORE RESULT

Write results to destination.
F
(Register or Memory)
D
Examples:
• Result of ADD is placed in destination register EA
• Result of memory load is placed in destination
register OP
• For store instruction, data is stored to memory
EX

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 Computer Programming TA C162

Instruction Set Architecture of LC-3

ISA = All of the programmer-visible components
and operations of the computer
• Memory organization
 Address space -- How may locations can be addressed?
– Address space: 216 locations (16-bit addresses)
 Addressability -- How many bits per location?
– Addressability: 16 bits
• Register set
 How many? What size?
 Eight general-purpose registers: R0 - R7 Each 16 bits wide
– Temporary storage, accessed in a single machine cycle
– Accessing memory generally takes longer than a single
cycle
 Other registers
– Not directly addressable, but used by (and affected by)
instructions
– PC (program counter), condition codes
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 Computer Programming TA C162

Instruction Set Architecture of LC-3 Cont…

Instruction set
• Opcodes
 15 opcodes
 Operate instructions: ADD, AND, NOT
 Data movement instructions: LD, LDI, LDR, LEA, ST, STR, STI
 Control instructions: BR, JSR/JSRR, JMP, RTI, TRAP

• Data types
 16-bit 2’s complement integer

• Addressing modes
 How is the location of an operand specified?
 Non-memory addresses: immediate, register
 Memory addresses: PC-relative, indirect, base+offset

ISA provides all information needed to write a program in machine

language

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Operate Instructions
Only three operations: ADD, AND, NOT

Source and destination operands are registers

• These instructions do not reference memory.
• ADD and AND can use “immediate” mode,
where one operand is hard-wired into the instruction.

Show dataflow diagram with each instruction.

• Illustrates when and where data moves to accomplish the
desired operation

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NOT (Register)

Note: Src and Dst

could be the same register.

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this zero means “register mode”

ADD/AND (Register)

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this one means “immediate mode”

ADD/AND (Immediate)

Note: Immediate field is

sign-extended.

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Let’s try Using Operate Instructions

With only ADD, AND, NOT…
1. How do we subtract?
i.e. A - B

2. How do we initialize a register to zero?

3. How do we copy from one register to another?

4. How do we OR? (Try your self)

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Solution 1
Assuming the values A and B are in R0 and R1
1001 001 001 111111
NOT R1 R1
R1 NOT(R1)

0 001 010 001 1 0000 1

ADD R2 R1 1
R2 - B

0001 010 000 0 00 010

ADD R2 R0 R2
R2 A + (-B)

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Solution 2

0101 010 010 1 00000

AND R2 R2

Register R2 is initialized to zero

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Solution 3

0101 010 010 1 00000

AND R2 R2 R2initialized to zero

0101 010 010 0 00 011

ADD R2 R2 R3
R2R2+R3
Contents of R3 are copied to R2

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