TECHNICAL SEMINAR PRESENTATION

National Institute of Science & Technology

POLYMER ON CHIP

Under the guidance of

Mr. Vivek Sharma

Advisor
Submitted by

Dillip Kumar Konhar EI200127183

DILLIP KUMAR KONHAR EI200127183

[1]

TECHNICAL SEMINAR PRESENTATION

National Institute of Science & Technology

INTRODUCTION Aim of improving microelectronics chip . Lower cost,increase the packing density (size)improve performance and reliability .

Polymer-chip process where the semiconductor chip is assembled

face down onto circuit board is ideal for size .why? There is no extra area needed for contacting on the sides of component . Performance is superior because length of connection is minimized .

DILLIP KUMAR KONHAR EI200127183

[2]

TECHNICAL SEMINAR PRESENTATION

National Institute of Science & Technology

SOLDERING PROCESS
Wafer arrives from IC mfr tested

Bumping

Dicing

Pick and place Polymer chip

Add flux to substrate

A

Place on tape reel Or wafer pack l

Reflow

Clean

Underfill

Complete

Underfill cure

DILLIP KUMAR KONHAR EI200127183

[3]

TECHNICAL SEMINAR PRESENTATION

POLYMER CHIP PROCESS
National Institute of Science & Technology By soldering joining

By thermocompression
Thermosonic joining

DILLIP KUMAR KONHAR EI200127183

[4]

TECHNICAL SEMINAR PRESENTATION

National Institute of Science & Technology

POLYMER CHIP JOINING BY USING ADHESIVES Isotropic adhesive Anisotropic adhesive Nonconductive adhesive

DILLIP KUMAR KONHAR EI200127183

[5]

TECHNICAL SEMINAR PRESENTATION

National Institute of Science & Technology

DIFFERENT TYPES OF JOINTS

DILLIP KUMAR KONHAR EI200127183

[6]

TECHNICAL SEMINAR PRESENTATION

National Institute of Science & Technology

DISADVANTAGES

Difficult testing of bare dies .

Limited availability of bumped chip.

Repairing is difficult or impossible . Handling of bare chips is difficult .

High assembly accuracy needed . Material underfilling with curing time is needed .

DILLIP KUMAR KONHAR EI200127183

[7]

TECHNICAL SEMINAR PRESENTATION

National Institute of Science & Technology

ADVANTAGES Smaller size Increased functionality Improved performance Improved thermal capabilities Improved reliability

Low cost .

DILLIP KUMAR KONHAR EI200127183

[8]

TECHNICAL SEMINAR PRESENTATION

National Institute of Science & Technology

FABRICATION Polymer pillars fabricated directly on semiconductor chip Integrated with passive devices Radius and length are illuminated 30nm Ti and 700nm Au layers in photolithography pattern. Center-to-center spacing is 325 m Thin silicon nitride deposited.

DILLIP KUMAR KONHAR EI200127183

[9]

TECHNICAL SEMINAR PRESENTATION

National Institute of Science & Technology

Relative cost comparison Bumping cost. Assembly process cost . Die bumping cost . Cost of substrate .

Availability of components
Bumped chip or bare die . Soldering bump .

Synthetic flavours. Synthetic microfibers . Composite materials . DILLIP KUMAR KONHAR EI200127183

[10]

TECHNICAL SEMINAR PRESENTATION

National Institute of Science & Technology

SMART MATERIALS

Shape memory alloys .

Liquid crystal in coated fabrics . Thermochronic dyes .

Modified starches .
Cellular carbon and kevlar . Teflon .

DILLIP KUMAR KONHAR EI200127183

[11]

TECHNICAL SEMINAR PRESENTATION

National Institute of Science & Technology

MODERN MATERIALS FOR POLYMER

Polycapralactone .
Lenticullar sheet . Shape memory alloy (SMA) .

Thermochronic film .

DILLIP KUMAR KONHAR EI200127183

[12]

TECHNICAL SEMINAR PRESENTATION

National Institute of Science & Technology

CONCLUSION Polymer chip based devise coupled to the API 3000 mass spectrometer . The device can be used for proteomic research . Characteristic of PDs do not degrade in fabrication . Future fabrication can be done both electrical and optical polymer . Lateral compliance minimizes optical losses due to offset and enhanced chip reliability .

THANK YOU !!

DILLIP KUMAR KONHAR EI200127183

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