RTOS

Preemptive fixed priority policy
S1
time period T1 = 2
execution time C1= 1

S1
time period T1 = 2
S2
time period T2 = 5

S1
time period T1 = 2
S2
time period T2 = 5
LCM ( 5 , 2 ) = 10

S1
time period T1 = 2
S2
time period T2 = 5
LCM ( 5 , 2 ) = 10
T2 = 5

S1
time period T1 = 2
S2
time period T2 = 5
LCM ( 5 , 2 ) = 10
T2 = 5
T2 = 5

S1
time period T1 = 2
S2
time period T2 = 5
LCM ( 5 , 2 ) = 10
T1 = 2
T2 = 5
T2 = 5

S1
time period T1 = 2
S2
time period T2 = 5
LCM ( 5 , 2 ) = 10
T1 = 2
T1 = 2
T2 = 5
T2 = 5

S1
time period T1 = 2
S2
time period T2 = 5
LCM ( 5 , 2 ) = 10
T1 = 2
T1 = 2
T2 = 5
T1 = 2
T1 = 2
T2 = 5
T1 = 2

S1
time period T1 = 2
S2
time period T2 = 5
LCM ( 5 , 2 ) = 10
T1 = 2
T1 = 2
T2 = 5
PRIOR(S1) > PRIOR(S2)
T1 = 2
T1 = 2
T2 = 5
T1 = 2

S1
time period T1 = 2
S2
time period T2 = 5
LCM ( 5 , 2 ) = 10
S1
S2
T1 = 2
T1 = 2
T2 = 5
T1 = 2
T1 = 2
T2 = 5
T1 = 2

S1
time period T1 = 2
S2
time period T2 = 5
LCM ( 5 , 2 ) = 10
S1
S2
T1 = 2
T1 = 2
T2 = 5
T1 = 2
T1 = 2
T2 = 5
T1 = 2

S1
time period T1 = 2
S2
time period T2 = 5
LCM ( 5 , 2 ) = 10
S1
S2
T1 = 2
T1 = 2
T2 = 5
T1 = 2
T1 = 2
T2 = 5
T1 = 2

S1
time period T1 = 2
S2
time period T2 = 5
LCM ( 5 , 2 ) = 10
S1
S2
T1 = 2
T1 = 2
T2 = 5
T1 = 2
T1 = 2
T2 = 5
T1 = 2

S1
time period T1 = 2
S2
time period T2 = 5
LCM ( 5 , 2 ) = 10
S1
S2
T1 = 2
T1 = 2
T2 = 5
T1 = 2
T1 = 2
T2 = 5
T1 = 2

S1
time period T1 = 2
S2
time period T2 = 5
LCM ( 5 , 2 ) = 10
S1
S2
T1 = 2
T1 = 2
T2 = 5
T1 = 2
T1 = 2
T2 = 5
T1 = 2

S1
time period T1 = 2
S2
time period T2 = 5
LCM ( 5 , 2 ) = 10
S1
S2
T1 = 2
T1 = 2
T2 = 5
T1 = 2
T1 = 2
T2 = 5
T1 = 2

S1
time period T1 = 2
S2
time period T2 = 5
LCM ( 5 , 2 ) = 10
S1
S2
T1 = 2
T1 = 2
T2 = 5
T1 = 2
T1 = 2
T2 = 5
T1 = 2

U = 1/T1 + 1/ T2
S1
S2
time period T1 = 2
time period T2 = 5

LCM ( 5 , 2 ) = 10
= +1/5
= 0.7
S1
S2
T1 = 2
T1 = 2
T2 = 5
T1 = 2
T1 = 2
T2 = 5
T1 = 2
INCREASE THE EXECUTION TIME

U = 1/T1 + 1/ T2
S1
S2
time period T1 = 2
time period T2 = 5

LCM ( 5 , 2 ) = 10
= +1/5
= 0.7
S1
S2
T1 = 2
T1 = 2
T2 = 5
T1 = 2
T1 = 2
T2 = 5
T1 = 2

U = 1/T1 + 1/ T2
S1
S2
time period T1 = 2
time period T2 = 5

LCM ( 5 , 2 ) = 10
= +2/5
= 0.9
S1
S2
T1 = 2
T1 = 2
T2 = 5
T1 = 2
T1 = 2
T2 = 5
T1 = 2

U = 1/T1 + 1/ T2
S1
S2
time period T1 = 2
time period T2 = 5
LCM ( 5 , 2 ) = 10
= +2/5
= 0.9

Releases of S1 during T2 is T2 / T1 = 5/2 = 3
S1
S2
T1 = 2
T1 = 2
T2 = 5
T1 = 2
T1 = 2
T2 = 5
T1 = 2
RM policy overload scenario
Example 1
T1
T2
T3
Example 1
T1
C1
T2
C2
T3
C3
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
LCM = 70
U total = 0.98
Example 1
RM SCHEDULE
S1
S2
S3
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
LCM = 70
U total = 0.98
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
RM SCHEDULE
S1
S2
S3
T3
LCM = 70
U total = 0.98
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
RM SCHEDULE
S1
S2
S3
T2
T3
LCM = 70
U total = 0.98
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
RM SCHEDULE
S1
S2
S3
T1
T2
T3
LCM = 70
U total = 0.98
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
RM SCHEDULE
S1
S2
S3
T1
T2
T3
LCM = 70
U total = 0.98
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
RM SCHEDULE
S1
S2
S3
T1
T2
T3
LCM = 70
U total = 0.98
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
RM SCHEDULE
S1
S2
S3
T1
T2
T3
LCM = 70
U total = 0.98
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
RM SCHEDULE
S1
S2
S3
T1
T2
T3
LCM = 70
U total = 0.98
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
RM SCHEDULE
S1
S2
S3
T1
T2
T3
LCM = 70
U total = 0.98
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
RM SCHEDULE
S1
S2
S3
T1
T2
T3
LCM = 70
U total = 0.98
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
RM SCHEDULE
S1
S2
S3
T1
T2
T3
LCM = 70
U total = 0.98
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
RM SCHEDULE
S1
S2
S3
T1
T2
T3
LCM = 70
U total = 0.98
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
RM SCHEDULE
S1
S2
S3
T1
T2
T3
LCM = 70
U total = 0.98
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
RM SCHEDULE
S1
S2
S3
T1
T2
T3
LCM = 70
U total = 0.98
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
RM SCHEDULE
S1
S2
S3
T1
T2
T3
LCM = 70
U total = 0.98
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
RM SCHEDULE
S1
S2
S3
T1
T2
T3
LCM = 70
U total = 0.98
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
RM SCHEDULE
S1
S2
S3
T1
T2
T3
LCM = 70
U total = 0.98
Example 1
LCM = 70
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
U total = 0.98
RM SCHEDULE
S1
S2
S3
T1
T2
T3
Misses the
deadline
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
T1
T2
T3
S1
S2
S3
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
EDF SCHEDULE
LCM = 70
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
T1
T2
T3
S1
S2
S3
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
EDF SCHEDULE
LCM = 70
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
T1
T2
T3
S1
S2
S3
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
EDF SCHEDULE
LCM = 70
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
T1
T2
T3
S1
S2
S3
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
EDF SCHEDULE
LCM = 70
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
T1
T2
T3
S1
S2
S3
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
EDF SCHEDULE
LCM = 70
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
T1
T2
T3
S1
S2
S3
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
EDF SCHEDULE
LCM = 70
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
T1
T2
T3
S1
S2
S3
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
EDF SCHEDULE
LCM = 70
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
T1
T2
T3
S1
S2
S3
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
EDF SCHEDULE
LCM = 70
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
T1
T2
T3
S1
S2
S3
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
EDF SCHEDULE
LCM = 70
Completes
within the
deadline
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
T1
T2
T3
S1
S2
S3
TTD
S1
S2
S3
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
EDF SCHEDULE
LCM = 70
Completes
within the
deadline
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
T1
T2
T3
EDF SCHEDULE
S1
S2
S3
TTD
S1
S2
S3
LCM = 70
Completes
within the
deadline
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
T1
T2
T3
Completes
within the
deadline
EDF SCHEDULE
S1
S2
S3
TTD
S1
S2
S3
LCM = 70
2
5
X
4
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
T1
T2
T3
Completes
within the
deadline
EDF SCHEDULE
S1
S2
S3
TTD
S1
S2
S3
LCM = 70
2
5
7
X
4
6
X
5
X
4
X
3
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
T1
T2
T3
Completes
within the
deadline
EDF SCHEDULE
S1
S2
S3
TTD
S1
S2
S3
LCM = 70
2
5
7
X
4
6
2
X
5
X
X
4
X
3
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
LCM = 70
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
T1
T2
T3
Completes
within the
deadline
EDF SCHEDULE
S1
S2
S3
TTD
S1
S2
S3
2
5
7
X
4
6
2
X
5
X
X
4
2
X
3
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
LCM = 70
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
T1
T2
T3
EDF SCHEDULE
S1
S2
S3
Comp
within
dead
TTD
S1
S2
S3
2
5
7
X
4
6
2
X
5
X
X
4
2
X
3
X
5
2
2
4
X
X
3
2
X
X
X
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
LCM = 70
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
T1
T2
T3
EDF SCHEDULE
S1
S2
S3
Comp
within
dead
TTD
S1
S2
S3
2
5
7
X
4
6
2
X
5
X
X
4
2
X
3
X
5
2
2
4
X
X
3
7
2
X
6
X
X
5
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
LCM = 70
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
T1
T2
T3
EDF SCHEDULE
S1
S2
S3
Comp
within
dead
TTD
S1
S2
S3
2
5
7
X
4
6
2
X
5
X
X
4
2
X
3
X
5
2
2
4
X
X
3
7
2
X
6
X
X
5
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
T1
T2
T3
S1
S2
S3
laxity
S1
S2
S3
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
LLF SCHEDULE
LCM = 70
Completes
within the
deadline
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
T1
T2
T3
LLF SCHEDULE
S1
S2
S3
laxity
S1
S2
S3
LCM = 70
Completes
within the
deadline
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
T1
T2
T3
LLF SCHEDULE
S1
S2
S3
Executed
once
laxity
S1
S2
S3
LCM = 70
Completes
within the
deadline
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
T1
T2
T3
Completes
within the
deadline
LLF SCHEDULE
S1
S2
S3
Executed
once
laxity
S1
S2
S3
LCM = 70
1
4
x
3
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
T1
T2
T3
Completes
within the
deadline
LLF SCHEDULE
S1
S2
S3
Executed
twice
laxity
S1
S2
S3
LCM = 70
1
4
5
x
3
4
x
3
x
2
x
2
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
LCM = 70
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
T1
T2
T3
Completes
within the
deadline
LLF SCHEDULE
S1
S2
S3
Executed
twice
laxity
S1
S2
S3
1
4
5
x
3
4
1
x
3
x
x
2
1
x
2
x
1
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
LCM = 70
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
T1
T2
T3
Completes
within the
deadline
LLF SCHEDULE
S1
S2
S3
Executed
twice
laxity
S1
S2
S3
1
4
5
x
3
4
1
x
3
x
x
2
1
x
2
x
4
1
1
3
x
x
1
x
x
x
Example 1
T1
C1
U1
0.5
T2
C2
U2
0.2
T3
C3
U3
0.28
LCM = 70
U total = 0.98
Misses the
deadline
RM SCHEDULE
S1
S2
S3
T1
T2
T3
Completes
within the
deadline
LLF SCHEDULE
S1
S2
S3
Executed
twice
laxity
S1
S2
S3
1
4
5
x
3
4
1
x
3
x
x
2
1
x
2
x
4
1
1
3
x
x
2
5
1
x
4
x
x
3
Hamming encoding
1) If check bits = 0 & parity encoded word =0 then NO
ERRORS
Hamming encoding
ERRORS
2) If check bits ! = 0 & parity encoded word =1 then SINGLE
BIT ERROR CAN CORRECT
Hamming encoding
ERRORS
3) If check bits ! = 0 & parity encoded word =0 then MULTI BIT
ERROR DETECTED HALT
Hamming encoding
ERRORS
3) If check bits ! = 0 & parity encoded word =0 then MULTI BIT
ERROR DETECTED HALT
4) If check bits = 0 & parity encoded word =1 then PARITY

ERROR CAN CORRECT
DATA = 11000100
0
PW
ED
10
11
12
DATA = 11000100
ED
PW
P01
10
11
12
DATA = 11000100
ED
PW
P01
P02
10
11
12
DATA = 11000100
ED
PW
P01
P02
4
P03
10
11
12
DATA = 11000100
ED
PW
P01
P02
4
P03
8
P04
10
11
12
DATA = 11000100
ED
PW
P01
P02
4
P03
8
P04
10
11
12
DATA = 11000100
ED
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
DATA = 11000100
ED
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0
0 1 0 0
DATA = 11000100
0
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0 0 X 0 1 0 0
ED
DATA = 11000100
0
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0 0 X 0 1 0 0
P01
P02
P03
P04
ED
DATA = 11000100
0
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0 0 X 0 1 0 0
P01
P02
P03
P04
ED
DATA = 11000100
0
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0 0 X 0 1 0 0
P01
X
P02
P03
P04
ED
DATA = 11000100
0
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0 0 X 0 1 0 0
P01
X
1
1
0
0
0
P02
P03
P04
ED
DATA = 11000100
Even number of 1s
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0 0 X 0 1 0 0
P01
X
1
1
0
0
0
P02
P03
P04
ED
DATA = 11000100
Even number of 1s
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0 0 X 0 1 0 0
P01
0
1
1
0
0
0
P02
P03
P04
ED
DATA = 11000100
P01 =0
0
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0 0 X 0 1 0 0
P01
0
1
1
0
0
0
P02
P03
P04
ED
DATA = 11000100
P01 =0
0
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0 0 X 0 1 0 0
P01
0
1
1
0
0
0
P02
P03
P04
ED
DATA = 11000100
P01 =0
0
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0 0 X 0 1 0 0
P01
0
1
1
0
0
0
P02
P03
P04
ED
DATA = 11000100
P01 =0
0
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0 0 X 0 1 0 0
P01
0
1
1
0
0
0
P02
P03
P04
ED
DATA = 11000100
P01 =0
0
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0 0 X 0 1 0 0
P01
0
1
1
0
0
0
P02
X
P03
P04
ED
DATA = 11000100
P01 =0
0
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0 0 X 0 1 0 0
P01
0
1
1
0
0
0
P02
X 1
0 0
0 1
P03
P04
ED
DATA = 11000100
P01 =0
0
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0 0 X 0 1 0 0
P01
0
1
1
0
0
0
P02
0 1
0 0
0 1
P03
P04
ED
DATA = 11000100
P01 =0
P02 =0
0
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0 0 X 0 1 0 0
P01
0
1
1
0
0
0
P02
0 1
0 0
0 1
P03
P04
ED
DATA = 11000100
P01 =0
P02 =0
0
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0 0 X 0 1 0 0
P01
0
1
1
0
0
0
P02
0 1
0 0
0 1
P03
P04
ED
DATA = 11000100
P01 =0
P02 =0
0
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0 0 X 0 1 0 0
P01
0
1
1
0
0
0
P02
0 1
0 0
0 1
P03
P04
ED
DATA = 11000100
P01 =0
P02 =0
0
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0 0 X 0 1 0 0
P01
0
1
1
0
0
0
P02
0 1
0 0
0 1
P03
X
P04
ED
DATA = 11000100
P01 =0
Odd number of 1s
P02 =0
0
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0
P01
0
1
1
P02
0 1
0
P03
X 1 0
P04
ED
0 X 0 1 0 0
0
0
0
0
0 1
0
0
DATA = 11000100
P01 =0
P02 =0
P03 =1
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0
P01
0
1
1
P02
0 1
0
P03
1 1 0
P04
ED
0 X 0 1 0 0
0
0
0
0
0 1
0
0
DATA = 11000100
P01 =0
P02 =0
P03 =1
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0
P01
0
1
1
P02
0 1
0
P03
1 1 0
P04
ED
0 X 0 1 0 0
0
0
0
0
0 1
0
0
DATA = 11000100
P01 =0
P02 =0
P03 =1
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0
P01
0
1
1
P02
0 1
0
P03
1 1 0
P04
ED
0 X 0 1 0 0
0
0
0
0
0 1
0
0
x
DATA = 11000100
P01 =0
P02 =0
P03 =1
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0
P01
0
1
1
P02
0 1
0
P03
1 1 0
P04
ED
0 X 0 1 0 0
0
0
0
0
0 1
0
0
x 0 1 0 0
DATA = 11000100
P01 =0
P02 =0
P03 =1
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0
P01
0
1
1
P02
0 1
0
P03
1 1 0
P04
ED
0 X 0 1 0 0
0
0
0
0
0 1
0
0
1 0 1 0 0
DATA = 11000100
P01 =0
P02 =0
P03 =1
P04 =1
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0
P01
0
1
1
P02
0 1
0
P03
1 1 0
P04
ED
0 X 0 1 0 0
0
0
0
0
0 1
0
0
1 0 1 0 0
DATA = 11000100
P01 =0
P02 =0
P03 =1
P04 =1
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0
P01
0
1
1
P02
0 1
0
P03
1 1 0
P04
ED
0 X 0 1 0 0
0
0
0
0
0 1
0
0
1 0 1 0 0
DATA = 11000100
P01 =0
P02 =0
P03 =1
P04 =1
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0
P01
0
1
1
P02
0 1
0
P03
1 1 0
P04
ED
0 X 0 1 0 0
0
0
0
0
0 1
0
0
1 0 1 0 0
DATA = 11000100
P01 =0
P02 =0
P03 =1
P04 =1
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0
P01
0
1
1
P02
0 1
0
P03
1 1 0
P04
ED
0 X 0 1 0 0
0
0
0
0
0 1
0
0
1 0 1 0 0
DATA = 11000100
P01 =0
P02 =0
P03 =1
P04 =1
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0
P01
0
1
1
P02
0 1
0
P03
1 1 0
P04
ED
0 0
0 X 0 1 0 0
0
0
0
0
0 1
0
0
1 0 1 0 0
DATA = 11000100
P01 =0
P02 =0
P03 =1
P04 =1
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0
P01
0
1
1
P02
0 1
0
P03
1 1 0
P04
ED
0 X 0 1 0 0
0
0
0
0
0 1
0
0
1 0 1 0 0
0 0 1 1 1 0 0 1 0 1 0 0
DATA = 11000100
P01 =0
P02 =0
P03 =1
P04 =1
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
D X X X 1 X 1 0
P01
0
1
1
P02
0 1
0
P03
1 1 0
P04
Parity of word
number of 1s odd
ED
0 X 0 1 0 0
0
0
0
0
0 1
0
0
1 0 1 0 0
1 0 0 1 1 1 0 0 1 0 1 0 0
Hamming encoding for 8bit word with no error in computed

syndrome
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0

syndrome
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0

syndrome
SYN
ED
C01
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0
0
C02
C03
C04
CD

syndrome
SYN
ED
C01
PW
P01
P02
D01
C03
C04
CD
Number
of 1s even
P03 D02 D03
so check bit =0
10
11
12
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0
0
C02

syndrome
SYN
ED
C01
C02
C03
C04
CD
PW
P01
P02
D01
Number
of 1s even
P03 D02 D03
so check bit =0
10
11
12
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0
0

syndrome
SYN
ED
C01
C02
C03
C04
CD
PW
P01
P02
D01
Number
of 1s even
P03 D02 D03
so check bit =0
10
11
12
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0
0

syndrome
SYN
ED
C01
C02
C03
C04
CD
PW
P01
P02
D01
Number
of 1s even
P03 D02 D03
so check bit =0
10
11
12
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0
0

syndrome
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0

syndrome
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0

syndrome
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0

syndrome
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0

syndrome
SYN
ED
C01
C02
C03
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 1 1 1
C04
CD

syndrome
SYN
ED
C01
0
0
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 1 1 1

syndrome
SYN
ED
C01
0
0
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 1 1 1

syndrome
SYN
ED
C01
0
0
C02
C03
C04
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 1 1 1
0
1 0 1 0 0
CD

syndrome
SYN
ED
C01
0
0
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 1 1 1
0
1 0 1 0 0

syndrome
SYN
ED
C01
0
0
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 1 1 1
0
1 0 1 0 0
0 0 1 1 1 0 0 1 0 1 0 0

syndrome
SYN
ED
C01
0
0
C02
C03
C04
0
0
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 1 1 1
Parity of word
number of 1s is
even
0
1 0 1 0 0
1 0 0 1 1 1 0 0 1 0 1 0 0

syndrome
SYN
ED
C01
0
0
C02
C03
C04
0
0
PW
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 1 1 1
0
1 0 1 0 0
1 0 0 1 1 1 0 0 1 0 1 0 0

ERRORS
SBE
SBE detection & correction
SYN
ED
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0
C01
C02
DATA IS CORRUPTED
DUE TO ELECTRO
MAGNETIC
INTERFACE
C03
C04
CD
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
SYN
ED
C01
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
0
C02
C03
C04
CD
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
0
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
0
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
0
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
SYN
ED
C01
1
0
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
SYN
ED
C01
1
0
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
SYN
ED
C01
1
0
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
SYN
ED
C01
1
0
C02
C03
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 0 0 0
C04
CD
SYN
ED
C01
1
0
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 0 0 0
SYN
ED
C01
1
0
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 0 0 0
SYN
ED
C01
1
0
C02
C03
C04
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 0 0 0
0
1 0 1 0 0
CD
SYN
ED
C01
1
0
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 0 0 0
0
1 0 1 0 0
0 0 1 1 0 0 0 1 0 1 0 0
SYN
ED
C01
1
0
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 0 0 0
ODD number of 1s
0
1 0 1 0 0
1 0 0 1 1 0 0 0 1 0 1 0 0
SYN
ED
C01
1
0
C02
C03
C04
0
1
PW
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 0 0 0
ODD number of 1s
0
1 0 1 0 0
1 0 0 1 1 0 0 0 1 0 1 0 0
2) If check bits! = 0 & parity encoded word =1 then SBE

ERROR , CAN BE CORRECTED
C4C3C2C1 = 0101 = 5
SYN
ED
C01
1
0
C02
C03
C04
0
1
PW
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 0 0 0
0
1 0 1 0 0
1 0 0 1 1 0 0 0 1 0 1 0 0
SYN
ED
C01
1
0
C02
C03
C04
0
1
PW
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 0 0 0
0
1 0 1 0 0
1 0 0 1 1 1 0 0 1 0 1 0 0
Hamming catches MBE but cannot

correct
SYN
ED
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0
C01
C02
DATA IS CORRUPTED
DUE TO ELECTRO
MAGNETIC
INTERFACE
C03
C04
CD
SYN
ED
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
C01
C02
DATA IS CORRUPTED
DUE TO ELECTRO
MAGNETIC
INTERFACE
C03
C04
CD
SYN
ED
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 0 1 0 0
C01
C02
DATA IS CORRUPTED
DUE TO ELECTRO
MAGNETIC
INTERFACE
C03
C04
CD
SYN
ED
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 1 1 0 0
C01
C02
DATA IS CORRUPTED
DUE TO ELECTRO
MAGNETIC
INTERFACE
C03
C04
CD
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 1 1 0 0
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 1 1 0 0
SYN
ED
C01
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 1 1 0 0
0
C02
C03
C04
CD
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 1 1 0 0
0
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 1 1 0 0
0
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 1 1 0 0
0
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 1 1 0 0
0
1
0 0
0
0
1
0 0 0 1
SYN
ED
C01
0
1
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 1 1 0 0
0
1
0 0
0
0
1
0 0 0 1
SYN
ED
C01
0
1
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 1 1 0 0
0
1
0 0
0
0
1
0 0 0 1
SYN
ED
C01
0
1
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 1 1 0 0
0
1
0 0
0
0
1
0 0 0 1
SYN
ED
C01
0
1
C02
C03
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 1 1 0 0
0
1
0 0
0
0
1
0 0 0 1
1 0 0 0
C04
CD
SYN
ED
C01
0
1
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 1 1 0 0
0
1
0 0
0
0
1
0 0 0 1
1 0 0 0
SYN
ED
C01
0
1
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 1 1 0 0
0
1
0 0
0
0
1
0 0 0 1
1 0 0 0
SYN
ED
C01
0
1
C02
C03
C04
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 1 1 0 0
0
1
0 0
0
0
1
0 0 0 1
1 0 0 0
0
1 1 1 0 0
CD
SYN
ED
C01
0
1
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 1 1 0 0
0
1
0 0
0
0
1
0 0 0 1
1 0 0 0
0
1 1 1 0 0
SYN
ED
C01
0
1
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 1 1 0 0
0
1
0 0
0
0
1
0 0 0 1
1 0 0 0
0
1 1 1 0 0
1 0 0 1 1 0 0 0 1 1 1 0 0
SYN
ED
C01
0
1
C02
C03
C04
1
0
PW
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 0 0 0 1 1 1 0 0
0
1
0 0
0
0
1
0 0 0 1
1 0 0 0
0
1 1 1 0 0
1 0 0 1 1 0 0 0 1 1 1 0 0
3) If check bits! = 0 & parity encoded word =0 then MBE

DETECTED , HALT
PARITY ERROR
SYN
ED
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
1 0 0 1 1 1 0 0 1 0 1 0 0
C01
C02
PARITY BIT GETS

CORRUPTED
C03
C04
CD
SYN
ED
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
0 0 0 1 1 1 0 0 1 0 1 0 0
C01
C02
PARITY BIT GETS

CORRUPTED
C03
C04
CD
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
0 0 0 1 1 1 0 0 1 0 1 0 0
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
0 0 0 1 1 1 0 0 1 0 1 0 0
SYN
ED
C01
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
0 0 0 1 1 1 0 0 1 0 1 0 0
0
C02
C03
C04
CD
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
0 0 0 1 1 1 0 0 1 0 1 0 0
0
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
0 0 0 1 1 1 0 0 1 0 1 0 0
0
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
0 0 0 1 1 1 0 0 1 0 1 0 0
0
SYN
ED
C01
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
0 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
SYN
ED
C01
0
0
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
0 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
SYN
ED
C01
0
0
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
0 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
SYN
ED
C01
0
0
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
0 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
SYN
ED
C01
0
0
C02
C03
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
0 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 1 0 0
C04
CD
SYN
ED
C01
0
0
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
0 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 1 0 0
SYN
ED
C01
0
0
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
0 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 1 0 0
SYN
ED
C01
0
0
C02
C03
C04
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
0 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 1 0 0
0
1 0 1 0 0
CD
SYN
ED
C01
0
0
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
0 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 1 0 0
0
1 0 1 0 0
SYN
ED
C01
0
0
C02
C03
C04
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
0 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 1 0 0
0
1 0 1 0 0
0 0 0 1 1 1 0 0 1 0 1 0 0
SYN
ED
C01
0
0
C02
C03
C04
0
1
PW
CD
10
11
12
PW
P01
P02
D01
P03
D02
D03
D04
P04
D05
D06
D07
D08
0 0 0 1 1 1 0 0 1 0 1 0 0
0
1
0 1
0
0
0 0 1 0
1 1 0 0
0
1 0 1 0 0
0 0 0 1 1 1 0 0 1 0 1 0 0
4) If check bits = 0 & parity encoded word =1 then Parity error

can correct

RTOS

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RTOS

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Доступные форматы

Preemptive fixed priority policy

execution time C1= 1

Preemptive fixed priority policy

execution time C1= 1

execution time C2= 1

Preemptive fixed priority policy

execution time C1= 1

execution time C2= 1

Preemptive fixed priority policy

execution time C1= 1

execution time C2= 1

Preemptive fixed priority policy

execution time C1= 1

execution time C2= 1

Preemptive fixed priority policy

execution time C1= 1

execution time C2= 1

Preemptive fixed priority policy

execution time C1= 1

execution time C2= 1

Preemptive fixed priority policy

execution time C1= 1

execution time C2= 1

Preemptive fixed priority policy

execution time C1= 1

execution time C2= 1

PRIOR(S1) > PRIOR(S2)

Preemptive fixed priority policy

execution time C1= 1

execution time C2= 1

PRIOR(S1) > PRIOR(S2)

Preemptive fixed priority policy

execution time C1= 1

execution time C2= 1

PRIOR(S1) > PRIOR(S2)

Preemptive fixed priority policy

execution time C1= 1

execution time C2= 1

PRIOR(S1) > PRIOR(S2)

Preemptive fixed priority policy

execution time C1= 1

execution time C2= 1

PRIOR(S1) > PRIOR(S2)

Preemptive fixed priority policy

execution time C1= 1

execution time C2= 1

PRIOR(S1) > PRIOR(S2)

Preemptive fixed priority policy

execution time C1= 1

execution time C2= 1

PRIOR(S1) > PRIOR(S2)

Preemptive fixed priority policy

execution time C1= 1

execution time C2= 1

PRIOR(S1) > PRIOR(S2)

Preemptive fixed priority policy

execution time C1= 1

execution time C2= 1

PRIOR(S1) > PRIOR(S2)

Preemptive fixed priority policy

execution time C1= 1

PRIOR(S1) > PRIOR(S2)

INCREASE THE EXECUTION TIME

Preemptive fixed priority policy