PRESENTATION OF MICROPROCESSOR

Submitted to Engr. M. Bux Alvi Submitted by RAHEELA KOUSAR (08CS02) AMBREEN GULL (08CS03) 5th semester Computer system Engineering UCET The Islamia University of style Bahawalpur Click to edit Master subtitle

TOPIC OF PRESENTATION
8086 to Click MICROPROCESSOR edit Master subtitle style INTERRUPTS

INTERRUPT
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Interrupt is an event which disturbs the normal execution of processor. When the microprocessor receives an interrupt signal, it suspend the currently executing program and jumps to an interrupt service routine (ISR) to respond to the incoming interrupt. Each interrupt has its own ISR.

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Responding to an interrupt may be immediate or delayed depending on whether the interrupt is maskable or non-maskable and whether interrupts are being masked or not.
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Maskable Interrupts (Can be delayed or Rejected) Non-Maskable Interrupts (Can not be delayed or Rejected)

TYPES OF INTERRUPTS
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8086 has three types of interrupts Software interrupts Hardware interrupts Processor interrupts

Software interrupts
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Software interrupts are used by programs to request a system services. A software interrupt occurs when a program calls an interrupt routine using the INT instruction. The format of the INT instruction is INT interrupt-number

EXAMPLE
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INT 3 is a software interrupt which is break point. (stop the execution at the desire position) Trace is also break point (this break point work after each line in the program)

STEPS TO INVOKE THE INT INSTRUCTION

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The number following the INT mnemonic tells the CPU which entry to locate in the interrupt vector table. The CPU pushes the flags on the stack, disables hardware interrupts and executes a call to the address stored in the IVT. The interrupt handler at this address begins execution and finishes when the IRET (interrupt return) instruction is reached. The IRET instruction causes the program to resume execution at the next instruction in the calling program.

HARDWARE INTERRUPTS
These are the interrupts initiated by external hardware . l 8086 has two pin reserved for it. 1. NMI 2. INTR
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NMI
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The rising edge of the signal on this pin causes a type 2 interrupt to be generated, and control is transferred to the corresponding ISR. This interrupt is used to shut the system down due to memory parity error.

INTR
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This pin allows external hardware to activate any of the 256 interrupts. With single input pin, processor seems to be limited to one hardware interrupts request. However using 8259 programmable interrupt controller (PIC) as many as 8 inputs can be accommodated.

PROCESSOR INTERRUPTS
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Generated by the processor itself. e.g type 0 interrupt occurs, when an attempt to divide by zero occur Interrupt 0D general protection fault. This interrupt will be generated whenever a protected mode program attempts to access data or code @ higher privilege level.

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Processor generates these interrupts automatically. However user via OS can write the corresponding service routine & place the address of these routine in IVT.

THANKS
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