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Conventional System Design Methodology ASIC/VLSI Design methodology - Logic Design - Physical Design - Fabrication Conclusion
Architecture Design Logic Design Physical Design Product Assembly Test Production Product
I N P U T
System
o U T P U T
Control
I N P U T
RAM
System
A/D
o U T P U T
Control
Logic Design
Product
Logic gates & Components
nets
IO Ports substrate
Test
Functional Design Parameters Environmental Reliability
VLSI Technology
ASIC
crosstalk Analysis
Architecture Design
Timing Analysis
Power Analysis
Functional Parameters Performance/Design Parameters -- Area -- Speed -- Power -- Noise Technology -- Complexity/Density -- Design Turnaround Time -- Design Methodology -- EDA Tools -- Process Technology -- Library -- Operating Conditions -- Cost
Moores Law
Microprocessors
PPC603 Pentium 80486 Pentium Pro PPC601 MIPS R4000 68040
10M
Transistors
1M
4004
17
18
Functionality
Technology
EDA Tools
Results (design productivity) Whats next?
Synthesis Cadence, Synopsys Schematic entry Daisy, Mentor, Valid Transistor entry Calma, Computervision, Magic
Design Abstraction
Algorithmic
Effectiveness
Gate-level
Reduce fan-out, capacitance Gate duplication, buffer insertion
Layout / Physical-Design
Move cells/gates around to shorten wires on critical
Level of detail
21
processors
ALUs , registers Logic gates
Transistors
Layout transistor Cells Chips / modules Circuit abstraction level Chips.MCM,boards Micro architecture abstraction level
Physical domain
Gate Array
FPGA
23
Technologies
ASIC
Structural Design
Logical Library
System Architecture
memwrite memread
controller
aluop[1:0]
alucontrol
funct[5:0]
alucontrol[2:0]
op[5:0]
zero
alusrca
alusrcb[1:0]
pcen
pcsource[1:0]
memtoreg
regdst
iord
regwrite
irwrite[3:0]
datapath
Design Hierarchy
Processor controller ALU Arithmetic Data Path
Logic
Sequencing
Divider
Full Adder
Half Adder
Multiplier
Half Adder
XOR
AND
XOR
AND
AND
OR
INV
AND
OR
INV
x g2 g4 y g3 z cout
a c
S= A+B+C
b c
I N P U T
Design
O U T P U T
CONTROL VECTORS
Functional Verification
A NAND B
A
Y
A Y B V s s
Library Components : Std.Cell around 400 Types various Drive Strengths - INV,NAND,AOI,FF,MUX,LATCHES etc Macros PLL,RAM,ROM,ADC etc IO Cells VDD,VSS, Clk, Data Bus etc.
Synthesis to Library
RTL Code
Synthesis Translation
Optimization Mapping Gate Level Netlist
What is Synthesis? Logic Synthesis is the automated process of converting a functional model of a system into a gate-level circuit.
HDL Source
Target Technology
Synthesis Flow
AND GATE
SYNTHESIS = TRANSILATION + OPTIMIZATION + MAPPING module and2 (z, a, b); output z; input a, b; always @ (a or b) if (a == 1 and b == 1) z <= 1; else z <= 0; endmodule a z b
OR GATE
TRANSILATION module or2 (z, a, b); output z; input a, b; a z b
OPTIMIZATION a z b
D-FLIP FLOP
module cnt (q, d, clk, rst);
output q; input d, clk, rst; reg q; always @ (posedge clk) if (rst) q <= 0; else q <= d; endmodule
COUNTER
module cnt (cout, clk, rst);
output [3:0] cout; input clk, rst; reg [3:0] cout; 0 always @ (posedge clk) if (rst) cout <= 4b0; else cout <= cout + 1b1; endmodule 0 1 clk 4 d q 4
+1
rst
You cannot rely solely on Tool to fix a poorly coded design. Try to understand the hardware you are describing, to give tool the best possible starting point.
Order and Group Arithmetic Functions The ordering and grouping of arithmetic functions can influence design performance. For Verilog, the following two statements are not necessarily equivalent. Statement1: ADD = A1 + A2 + A3 + A4; Statement2: ADD = (A1 + A2) + (A3 + A4); The second statement creates two adders in parallel: A1 + A2 and A3 + A4. In the second statement, the two additions are evaluated in parallel and the results are combined with a third adder. RTL simulation results are the same for both statements, however, the second statement results in a faster circuit after synthesis (depending on the bit width of the input signals).
In the second statement, the two additions are evaluated in parallel and the results are combined with a third adder.
Resource Sharing
Resource sharing is an optimization technique that uses a single functional block (such as an adder or comparator) to implement several operators in the HDL code. Use resource sharing to improve design performance by reducing the gate count and the routing congestion. If you do not use resource sharing, each HDL operation is built with separate circuitry. However, you may want to disable resource sharing for speed critical paths in your design.
Resource Sharing
Resource Sharing
Mapping
High-level synthesis is Constraint-Driven. High-level synthesis is based on design constraints and coding style Tool makes high-level synthesis decisions to produce areaefficient results that meet timing. High-level Synthesis takes place only when optimizing an unmapped design
Combinational mapping
Ripple Carry
Ripple Carry-Select
+
Carry Look Ahead
Carry Save
module Halfadder (a,b,sum,carry); input a,b; output sum, carry; wire sum, carry; assign sum = a^b; // sum bit assign carry = (a&b) ;//carry bit endmodule
Translation/Optimization - Gentech
Algorithmic . S = A XOR B = A. B + A. B C = A AND B = A . B
Schematic
A u1 u2 B D
u3 E
u4
S
Mapped to Technology
Design: Technology Mapped
Technology Library NOT Gate ANDL AND2L AND4L ANDXL
A N D 2L N O T L
A u1
u2 B
O R 2L
u3 E
A N D 4L
u4
S
OR Gate ORL OR2L OR4L ORXL AND Gate ANDL AND2L AND4L ANDXL AOI Gate --------
u1 u2 u3 u4 -
S A B ; D A B ; E S ; C D E ; -----
nets
End Module
instantiation