Hardware Description Languages

Basic Input/Output
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File Objects

VHDL objects: Signals, Variables, Constants, Files

Files provides an interface between the VHDL programs and the host environment
VHDL Program

file: type declaration operations

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Basic I/O Operations

File Type and Declaration Opening and Closing a File of a specified type Reading and Writing from a file
A very useful example of the application of file I/O is the construction of testbenches

Example: the testbench reads test inputs from a file, applies them to the model under test, and records model outputs for analysis
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File Type and Declaration

Files are distinguished by the type of information stored type textFileType is file of string; type integerFileType is file of integer; File declarations VHDL 1987 file infile: textFileType is in inputdata.txt; file outfile: textFileType is out outputdata.txt; File declarations VHDL 1993 file infile: textFileType open read_mode is inputdata.txt; file outfile: textFileType open write_mode is outputdata.txt;
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Binary File I/O (VHDL 1987)

--- test of binary file I/O -entity io87 is end io87; architecture beh of io87 is begin process type IntegerFileType is file of integer; file dataout:IntegerFileType is out output.txt; variable check :integer :=0; begin for count in 1 to 10 loop check := check+1; write(dataout, check); end loop; wait; end process; end beh;

VHDL 1987 provides read(f,value), write(f, value) and endfile(f) It uses implicit file open operations via file declarations
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Binary File I/O (VHDL 1993) cont.

entity io93 is end entity io93; architecture beh of io93 is begin process is type IntFileType is file of integer; -- file declarations file dataout :IntFileType; variable count : integer:= 0; variable fstatus: FILE_OPEN_STATUS; begin file_open(fstatus,dataout,"myfile.txt",write_mode); -- open the file for j in 1 to 8 loop write(dataout,count); -- some random values count := count+2; end loop; wait; -- an artificial way to stop the process end process; end architecture beh; 6

Binary File I/O (VHDL 1993) cont.

VHDL 93 provides READ(file_handle,value), WRITE(file_handle, value) and ENDFILE(file_handle), and also FILE_OPEN() and FILE_CLOSE() VHDL 93 allows both explicit and implicit file open operations procedure FILE_OPEN(file file_handle: FILE_TYPE File_name: in STRING; Open_kind: in FILE_OPEN_KIND := READ_MODE); procedure FILE_OPEN(File_Status:out FILE_OPEN_STATUS; file file_handle: FILE_TYPE File_name: in STRING; Open_kind: in FILE_OPEN_KIND := READ_MODE); procedure FILE_CLOSE(file file_handle: FILE_TYPE)
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Binary File I/O (VHDL 1993)

FILE_OPEN_KIND may have one of 3 values: READ_MODE, WRITE_MODE, APPEND_MODE

FILE_STATUS may have one of 4 values: OPEN_OK file open operation was successfull STATUS_ERROR attempted to open an already open file NAME_ERROR file not found MODE_ERROR file cannot be opened in this mode
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Binary File I/O limitations

The values passed on each line of the file are all of the same type It would be very handy to be able to pass different types ..

The TEXTIO Package

buffer writeline() line read(buf,c) write(buf,arg) line line line file

One common approach to I/O for the predefined types of the language is to use the TEXTIO package I/O is text based (ASCII) The TEXTIO package is in the STD library, which is implicitly declared. You do not need to declare the usage of the library STD, however you still need to declare the use of the package contents via the use clause
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The TEXTIO Package

Text based I/O A file is organized by lines read() and write() procedures operate on line data structures readline() and writeline() procedures transfer data from-to files The TEXTIO package is in the library STD and provides: procedures for reading and writing the pre-defined types from lines predefined access to std_input and std_output procedures names are overloaded procedure
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Example: Use of the TEXTIO Package

use std.textio.all; entity formatted_io is -- this entity is empty end formatted_io; architecture behavioral of formatted_io is begin process is file outfile :text; -- declare the file to be a text file variable fstatus :File_open_status; variable count: integer := 5; variable value : bit_vector(3 downto 0):= X6; variable buf: line; -- buffer to file begin -- open the file for writing file_open(fstatus, outfile,myfile.txt, write_mode); L1: write(buf, This is an example of formatted I/O); L2: writeline(outfile, buf); -- write buffer to file L3: write(buf, The First Parameter is =); L4: write(buf, count); L5: write(buf, ); L6: write(buf, The Second Parameter is = ); L7: write(buf, value); L8: writeline(outfile, buf); L9: write(buf, ...and so on); L10: writeline(outfile, buf); L11: file_close(outfile); -- flush the buffer to the file wait; end process; end architecture behavioral;

Result

This is an example of formatted I/O The First Parameter is = 5 The Second Parameter is = 0110 ...and so on 12

Passing Filenames interactively

process is variable buf : line; variable fname : string(1 to 10); begin --- prompt and read filename from standard input -write(output, Enter Filename: ); readline(input, buf); read(buf, fname); --- process code -end process;

Generally input and output are mapped to standard input and standard output respectively

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Extending TEXTIO for other Datatypes

Hide the ASCII format of TEXTIO from the user

Create type conversion procedures for reading and writing desired datatypes Encapsulate procedures in a package Install package in a library and make its contents visible via the use clause

library ieee; use ieee.std_logic_textio.all;

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Constructing Testbenches

General approach: Apply stimulus vectors and Measure and Record response vectors
If the number of test vectors is too big procedural vectors generation is preferable to FILE I/O vectors generation Clock and reset generation is usually done with procedural stimulus
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Testbenches: I/O stimulus generation example

... while not endfile(vectors) loop readline(vectors, vectorline); -- file format is 1011011 if (vectorline(1) = # then next; end if; read(vectorline, datavar); read((vectorline, A); -- A, B, and C are two bit vectors read((vectorline, B); -- of type std_logic read((vectorline, C); ---signal assignments Indata <= to_stdlogic(datavar); A_in <= unsigned(to_stdlogicvector(A)); -- A_in, B_in and C_in are B_in <= unsigned(to_stdlogicvector(B)); -- of unsigned vectors C_in <= unsigned(to_stdlogicvector(C)); wait for ClockPeriod; end loop; ... 16

Testbenches: Validation

Compare reference vectors with response vectors and record errors in external files In addition to failed tests record simulation time

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The ASSERT Statement

assert Q = check(1) and Qbar = check(0) report Test Vector Failed severity error;

Designer can report errors at predefined levels: NOTE, WARNING, ERROR and FAILURE (enumerated type) Report argument is a character string written to simulation output TEXTIO may be faster than ASSERT if we do not need to stop the simulation
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Summary

Basic Input/Output Binary I/O ASCII I/O and the TEXTIO package VHDL 87 vs. VHDL 93
Testbenches The ASSERT statement

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