Design and Implementation of ECG Amplifier with Active DC suppression

Akshay Mathur
Senior Undergraduate ICE Dept., NIT Jalandhar

Project Guide: Dr. Dilbag Singh Asst. Professor ICE Dept., NIT Jalandhar

Akshay Mathur

Introduction
ECG stands for Electrocardiogram which represents the electrical activity of heart. This signal is used to analyze the functional activity of heart and detection of various problems like arrhythmia and improper R-R interval

These signals need to be amplified before interfacing with some diagnostic machine or recording system since these signals are of very small magnitude
However, designing amplifiers for ECG signal require some special design because of the following problems:

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Introduction #2
Range of signals is very less: 0-5 mV. Output impedance is very high: several mega ohms DC offset voltage is observed due to half cell electrode, electrolyte polarization etc. These signals are superimposed with other biomedical signals like: ECG, EMG etc. These signals are easily superimposed with signals due to other devices like Magnetic Imaging Resonance, Power Frequencies

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Project Requirement
The problems discussed implies that signal cannot be amplified in single stage neither the gain can be set high in 1st stage to restrict the signal from entering into saturation stage. Hence the circuit to be designed requires following features: Amplification in two stages Rejection of higher frequency components Very high input impedance Very high common mode rejection ratio Suppression of DC offset voltage due to electrode gel polarization.
This project aims at designing an amplifier which includes all the features mentioned above.
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Proposed Scheme:
Features:
Amplifier output v=(Vin-KfV0/s)AD0 where AD0 represents the gain of IA High pass cut-off frequency fc = KfAD0/2 Kf = KRKiKAD

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Circuit Diagram

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Circuit Simulation

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Actual Testing Results

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Actual Testing Setup

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Developed Circuit #2

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Details of Circuit #2
First stage gain: Second stage gain: Overall gain: RC filter high pass frequency: Input impedance: CMRR: 25 32 800 0.05 Hz 2 M in series with 1.4 pF 80 db

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Testing results of circuit #2

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Testing results of circuit #2

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Future Work
Power frequency interference is too high which has to be necessarily removed. This may require a notch filter with 50 Hz frequency. Because of the improper leads used during testing of the circuit, there was a lot of noise in the system. So there is a requirement of using proper electrodes to connect the circuit to the electrodes.

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Questions & Comments

Akshay Mathur
Senior Undergraduate Department of Instrumentation & Control Engineering National Institute of Technology, Jalandhar India akshaymathur39@yahoo.com http://akshaymathur39.tripod.com
Phone: +91-9356481810, +91-129-3263175

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