Crosstalk Analysis

Vinit Patel - MT2012093 Yogesh Navik MT2012086

International Institute of Information Technology - Bangalore

Outline
Introduction Basics of Crosstalk
Noise and Delay Effects Timing Effects

Crosstalk Analysis
VLSI Design Flow Crosstalk Analysis Requirements Crosstalk Analysis Flow

Strategy for Fixing Crosstalk Violations

Introduction
Moores Law
This law had been quite practical from the time the first 4-bit microprocessor was introduced to the current days of Pentium processors.

Only possible by reducing the feature sizes of the CMOS Integrated Circuit. Feature sizes have moved from few micrometers to few nanometers. Very Deep Sub-Micron (VDSM) design phase.
below the feature sizes of 0.25mm (micrometer) fall into this category.

Challenges
Signal Integrity Issues
Crosstalk Delay Crosstalk Noise Ringing & Ground bounce IR (voltage) drop in power lines Electro-migration Manufacturing-related issues that if not addressed can lead to chip failure

According to the research conducted by Collett International Research Inc., in the year 2000, one in five chips fail because of the signal integrity issue

Basics of Crosstalk
Important Terms
Aggressor Victim

Types
Inductive Crosstalk Electrostatic Crosstalk

Crosstalk Metrics at Various Technology Nodes

The crosstalk problem becomes a severe problem as the geometries shrink below 0.25 m At smaller process technology geometries, the gate capacitance is insignificant when compared with wire capacitance. Because of this, the over-all timing path delays are dominated by interconnect delays, but not gate delays.

Coupling Capacitance vs. Substrate Capacitance

Noise and Delay Effects of Crosstalk

Timing Effects of Crosstalk Delay

Hold Violations Setup Violations

Timing Effects of Crosstalk Delay

Bus Violations

Crosstalk Analysis

Traditional VLSI Design Flow

Crosstalk Analysis Requirements Crosstalk Analysis Flow

Traditional VLSI Design Flow

Front-end flow : logical implementation of given design specification Back-end flow : translate the logical representation to physical representation that can be delivered for chip fabrication The next step is circuit parasitic extraction.

Crosstalk Analysis
Traditional VLSI Design Flow

Crosstalk Analysis Requirements

Crosstalk Analysis Flow

Crosstalk Analysis Requirement

Circuit parasitics form the basis for any crosstalk effect estimation. Detailed parasitic available only after completing the detailed routing of the design. Therefore, accurate crosstalk-analysis can be performed after the completion of both the signal and clock detailed routing steps.

Crosstalk Analysis
Traditional VLSI Design Flow Crosstalk Analysis Requirements

Crosstalk Analysis Flow

Crosstalk Analysis Flow

Step - 1

Coupled RC parasitics extraction using EDA Tools.

Generation of the Standard Delay Files(SDFs) Step - 2 Tool : PrimeTime

Static Timing Analysis with PrimeTime using the SDFs generated. Step - 3
Filtering of the crosstalk delay violations.

Step 4

Crosstalk Analysis Flow

Output of Layout Tool :
Library Exchange Formant (LEF) file Design Exchange Formant (DEF) file

These are inputs to the extraction tool Signal Parasitic Exchange Format (SPEF) file stores the RC parasitic info of all wires in the design. Crosstalk Delay Compensation for delay calculation.
Scale factors

Crosstalk Analysis Flow

Scale Factors

In coupling compensation, the distributed RC network along with coupling capacitances are first converted into an equivalent, lumped RC network. Multiplying the coupling capacitance with a dynamic scale factor performs the conversion.

Crosstalk Analysis Flow

After modifying the parasitics to take crosstalk into account : two crosstalk delay SDFs are generated.
Same direction switching delays Opposite direction switching delays

Static Timing Analysis : PrimeTime

Setup Analysis Hold Analysis

Filter Violations

STRATEGY FOR FIXING CROSSTALK VIOLATIONS

Analyzing and fixing the crosstalk violations is a highly iterative process. Several iterations are employed for identification and fixing of all the violations. Each of these iterations includes one or more methods to attack the problems.

Identification of Aggressors and Victims

A PERL script is used to parse the PrimeTime generated timing reports that contain all the crosstalk delay information. Another input for the script is the coupling capacitance information of all the wires in the design. The script then identifies various aggressors and victims based on the amount of delay effect caused by wire coupling.

Filtering of Static Wires

Static wires are the wires whose value does not change in the current operating mode. static wire examples include reset signals and boot- up configuration registers. static wires could safely be removed from the list of aggressors, since they do not really switch during normal operation.

Re-routing the Aggressors and Victims

attack the problem with minimal impact on the design. To see if the increased spacing rules is helpful by the tool. The re-routing aggressors and or victims method usually reduces the number of violations from as many as several hundreds to as little as few tens.

Up-sizing and Down-sizing

To up-size the cells (ex: buffers, inverters) that drive the victim wires in order to allow victim wires to have enough drive strength to reduce the effect of coupling from aggressor wires. A similar approach is to downsize cells that drive the aggressor paths in order to reduce their effect on the victim wires. The scenario in which the aggressor and the victim are mutually coupled to each other and they are aggressor and victim to each other, this method is not useful

Splitting the Long Aggressor and Victim Wires and Bus Shielding
The coupling capacitance caused by the aggressor is proportional to the length of the wire. The long interconnect wires can be carefully broken into multiple wires by inserting repeaters. The long interconnect bus signals between blocks can be shielded by Ground (VSS) wires on both sides of the bus, known as bus shielding.

Thank You !!