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Types of Testing

Criterion
When testing is performed? Where is the source of stimuli?

Attribute of testing method


*concurrently with normal system operation *As a separate activity *within the system *By external device *Design Errors *Fabrication errors *Fabrication Defects *Infancy physical failures *physical failures *IC *Board *System *In a fixed order *Depending upon results obtained so far *Slower than normal operation speed *At the normal operation speed *The entire output patterns *some function of output patterns Only the I/O lines I/O and internal lines *The system itself *An external device(Tester)

Terminology
*Online/Concurrent Testing *Off line Testing *Self Testing *External Testing *Design Verification Testing *Acceptance Testing *Burn In testing *Quality Assurance Testing *Field/Maintenance Testing *Component level Testing *Board level Testing *System level Testing *Ordered Testing *Adaptive Testing *DC(static) Testing *AC testing *Exhaustive testing *Compact Testing Edge Pin Testing Guided probe / Electron beam / In circuit Testing *Self checking/ Self Testing *External Testing

What do we test for?

What is the Physical object being tested? How are the stimuli applied? How fast the stimuli applied? What are the Observed results? What lines are accessible for testing Who checks the results

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Main Difficulties in Testing


Miniaturization
Physical access difficult or impossible.

Increasing complexity
Large amount of test data.

Number of access ports remains constant


Long test application time.

High speed
High demand on testers driver/sensor mechanism.

More complicated failure mechanism


The key to successful testing lies in the design process.
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Some Real Defects in Chips


Processing defects
Missing contact windows Parasitic transistors Oxide breakdown ...

Material defects

Time-dependent failures
Dielectric breakdown Electromigration ... Contact degradation Seal leaks ...

Bulk defects (cracks, crystal imperfections) Surface impurities (ion migration) ...

Packaging failures

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Errors and Faults

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An instance of an incorrect operation of the system being tested is referred to as an error. The causes of the errors may be:

## Design errors
examples of design errors are:
Incomplete or inconsistent specifications. Incomplete mapping between different levels of design. Violations of design rules.

## Physical faults
Physical faults can be fabrication errors, fabrication defects or physical failures.
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Fabrication errors occur due to:


Wrong components Incorrect wiring Shorts caused by improper soldering

Fabrication defects result from an imperfect manufacturing process.


Eg: shorts and opens are common defects.

Other fabrication defects are due to:


Improper doping profiles Mask alignment errors Poor encapsulation

Accurate location of fabrication defects is important in improving the manufacturing yield.


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Physical failures occur during the lifetime of a system due to component wear-out and/or environmental factors. eg: aluminum connectors inside an IC package thin out with time and may break because of electron migration or corrosion. Environmental factors such as temperature, humidity, vibrations and aging of components. #Fabrication errors, fabrication defects and physical failures are collectively called Physical faults. Physical faults can be classified as:
Permanent: always being present after their occurrence Intermittent: existing only during some intervals Transient: a one-time occurrence caused by a temporary change in some environmental factor.
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Physical failures appear early after fabrication is referred to as infancy failures. Physical faults do not allow a direct mathematical treatment of testing and diagnosis. The solution is to deal with logical faults (or fault models), which are a convenient representation of the effect of the physical faults on the operation of the system. Since a fault is detected by observing an error caused by it. The basic assumption regarding the nature of logical faults are referred to as fault model.
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How does a chip fail?


Usually failures are shorts between two conductors or opens in a conductor This can cause very complicated behavior

A simpler model: Stuck-At Assume all failures cause nodes to be stuck-at 0 or 1, i.e. shorted to GND or VDD Not quite true, but works well in practice

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Examples

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Observability & Controllability

Observability: ease of observing a node by watching external output pins of the chip Controllability: ease of forcing a node to 0 or 1 by driving input pins of the chip Combinational logic is usually easy to observe and control Finite state machines can be very difficult, requiring many cycles to enter desired state Especially if state transition diagram is not known to the test engineer

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Test Pattern Generation


Manufacturing test ideally would check every node in the circuit to prove it is not stuck. Apply the smallest sequence of test vectors necessary to prove each node is not stuck. Good observability and controllability reduces number of test vectors required for manufacturing test. Reduces the cost of testing Motivates design-for-test

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Modeling and Simulation As design errors precede the fabrication of the system, design verification testing can be performed by a testing experiment that uses a model of the designed system. A model means a digital computer representation of the system in terms of data structures and/or programs. The model can be exercised by simulating it with a representation of the input signals, the process is referred to as logic simulation.
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Test Evaluation
Test evaluation refers to determining the effectiveness or quality of a test.

Test evaluation is done in context of a fault model and quality of a test is measured by the ratio between the no of faults it detects and the total no of faults i.e., fault coverage. Fault coverage is measured as a percentage of the number of faults detected against the number of faults considered.
Test evaluation is carried out via a simulated testing experiment called fault simulation, which computes the response of the circuit in the presence of faults to the test being evaluated.
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Diagnosis and Repair


If the CUT or UUT or DUT found to be behaving incorrectly is to be repaired, the cause of the error must be diagnosed. Repair apply to design errors. Repair means Re-Design. Diagnosis does the manufacturing process optimization (reduce manufacturing errors). The term Diagnosis and Repair apply both to physical faults and to design errors.

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Fault Diagnosis Approaches


The fault diagnosis approaches are
Effect-cause analysis Cause-effect analysis

Effect-cause analysis (internal fault location):


Based on the erroneous response, determine directly the faults that could produce it.
Eg. guided-probe testing.

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Cause-effect analysis (external fault location):


Enumerates all possible faults existing in a fault model and determine, before the testing experiment, all their corresponding responses to a given applied test. The process that relies on fault simulation, builds a data base called a fault dictionary. The diagnosis is a dictionary look-up process, in which we try to match the actual response of the UUT with one of the precomputed responses. Cause-effect analysis does
Build a fault dictionary. Use dictionary look-up to determine the possible faults.

If the match is successful, the fault dictionary indicates the possible faults or faulty components in the UUT.
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Design for Testability (DFT)


Testability is a design characteristic that influences various costs associated with testing. DFT take into account the testing aspects during the design process so that more testable designs will be generated. DFT simplifies/automates test pattern generation, which decreases development cost and lead times. The design is changed to make it more testable. DFT techniques are design efforts specifically employed to ensure that a device is testable.
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Advantages of DFT are:


Reduce test efforts. Reduce cost for test equipments (ATE). Shorten turnaround time. Increase product quality.

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