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Criterion
When testing is performed? Where is the source of stimuli?
Terminology
*Online/Concurrent Testing *Off line Testing *Self Testing *External Testing *Design Verification Testing *Acceptance Testing *Burn In testing *Quality Assurance Testing *Field/Maintenance Testing *Component level Testing *Board level Testing *System level Testing *Ordered Testing *Adaptive Testing *DC(static) Testing *AC testing *Exhaustive testing *Compact Testing Edge Pin Testing Guided probe / Electron beam / In circuit Testing *Self checking/ Self Testing *External Testing
What is the Physical object being tested? How are the stimuli applied? How fast the stimuli applied? What are the Observed results? What lines are accessible for testing Who checks the results
3 May 2013
VTU Belgaum
Increasing complexity
Large amount of test data.
High speed
High demand on testers driver/sensor mechanism.
Material defects
Time-dependent failures
Dielectric breakdown Electromigration ... Contact degradation Seal leaks ...
Bulk defects (cracks, crystal imperfections) Surface impurities (ion migration) ...
Packaging failures
3 May 2013
VTU Belgaum
3 May 2013
VTU Belgaum
An instance of an incorrect operation of the system being tested is referred to as an error. The causes of the errors may be:
## Design errors
examples of design errors are:
Incomplete or inconsistent specifications. Incomplete mapping between different levels of design. Violations of design rules.
## Physical faults
Physical faults can be fabrication errors, fabrication defects or physical failures.
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Physical failures occur during the lifetime of a system due to component wear-out and/or environmental factors. eg: aluminum connectors inside an IC package thin out with time and may break because of electron migration or corrosion. Environmental factors such as temperature, humidity, vibrations and aging of components. #Fabrication errors, fabrication defects and physical failures are collectively called Physical faults. Physical faults can be classified as:
Permanent: always being present after their occurrence Intermittent: existing only during some intervals Transient: a one-time occurrence caused by a temporary change in some environmental factor.
VTU Belgaum
3 May 2013
Physical failures appear early after fabrication is referred to as infancy failures. Physical faults do not allow a direct mathematical treatment of testing and diagnosis. The solution is to deal with logical faults (or fault models), which are a convenient representation of the effect of the physical faults on the operation of the system. Since a fault is detected by observing an error caused by it. The basic assumption regarding the nature of logical faults are referred to as fault model.
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3 May 2013
VTU Belgaum
A simpler model: Stuck-At Assume all failures cause nodes to be stuck-at 0 or 1, i.e. shorted to GND or VDD Not quite true, but works well in practice
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Examples
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Observability: ease of observing a node by watching external output pins of the chip Controllability: ease of forcing a node to 0 or 1 by driving input pins of the chip Combinational logic is usually easy to observe and control Finite state machines can be very difficult, requiring many cycles to enter desired state Especially if state transition diagram is not known to the test engineer
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VTU Belgaum
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VTU Belgaum
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Modeling and Simulation As design errors precede the fabrication of the system, design verification testing can be performed by a testing experiment that uses a model of the designed system. A model means a digital computer representation of the system in terms of data structures and/or programs. The model can be exercised by simulating it with a representation of the input signals, the process is referred to as logic simulation.
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Test Evaluation
Test evaluation refers to determining the effectiveness or quality of a test.
Test evaluation is done in context of a fault model and quality of a test is measured by the ratio between the no of faults it detects and the total no of faults i.e., fault coverage. Fault coverage is measured as a percentage of the number of faults detected against the number of faults considered.
Test evaluation is carried out via a simulated testing experiment called fault simulation, which computes the response of the circuit in the presence of faults to the test being evaluated.
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If the match is successful, the fault dictionary indicates the possible faults or faulty components in the UUT.
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