MINOR PROJECT ON

DAY-WISE Digital alarm clock with PS/2 keyboard interfacing using FPGA KIT (VERILOG LANGUAGE)
Made by-

Rahul Sharma (10015002809)

Nidhi Joshi (10215002809)

Objectives achieved :Our objective of making a DAY-WISE DIGITAL ALARM CLOCK with PS/2 KEYBOARD INTERFACING using FPGA KIT has been achieved.

A Digital clock with a Progressive and Resettable alarm feature and display of time in a seven segment display has been achieved. And its Interfacing with PS/2 keyboard from where we can enter and set time is also working. Also a LED will glow when the clock time matches alarm time.

BLOCK DIAGRAM :PS/2 Keyboard Seven segment (to display time)

FPGA

When alarm time matches clock time

LED glows

PROJECT INCLUDES:

Clock dividers
Digital clock Alarm feature Ps/2 keyboard interfacing

Clock Divider

It is basically used to divide the frequency of clock n times. Frequency of Crystal oscillator of FPGA Kit is 50MHz and that of ps/2 Keyboard is 20 KHz. Therefore we have made a new clock signal ps2clk of 50mhz/20khz. Also, since FPGA Kit has 50Mhz clock frequency i.e. its time period is .02us and for our normal clock(used in watches, etc) we need 1sec time period. Hence, we have made clock divider of 50x 106 /50Mhz, i.e., 1sec.

Waveform of Digital Clock

divider

Waveform of Ps2 clock divider

Digital clock 00:00:01sec

Digital clock 00:01:00secs

Digital clock 01:00:00secs

RTL of Day-wise Alarm clock

Technology schematic of Day-wise digital alarm clock

Actual time of clock matches alarm time of MONDAY

Actual time of clock matches alarm time of TUESDAY

Actual time of clock matches new alarm time of MONDAY

Ps/2 State machine

1/0 Start bit 0/0 Count<9 1/1

data

Stop bit

Count=9

0/0

State machine

RTL of ps/2 INTERFACING

Value of store after 2nd bit of scan code is transmitted (serially) :-

Value of store after 3rd bit of scan code is transmitted (serially) :-

Value of store after 6th bit of scan code is transmitted (serially) :-

Successful transmission of 8-bit data(scan code)

Current status

Project is complete. Every module is working properly. Not been able to test it on hardware because of faulty FPGA Kit.

RESULT
DAY-WISE DIGITAL ALARM CLOCK with PS/2 KEYBOARD INTERFACING using FPGA KIT has been achieved.

FPGA kit

Seven segment display

Ps/2

When clock time matches alarm time

LED glows

References
http://www.scribd.com/doc/6868408/Clock-Dividers http://en.wikipedia.org/wiki/Field-programmable_gate_array http://www.xilinx.com/products/silicon-devices/fpga/xa-spartan-3e/index.htm http://en.wikipedia.org/wiki/Light-emitting_diode#Types

http://en.wikipedia.org/wiki/Seven-segment_display
http://www.controlengeurope.com/article/32043/Advantages-of-FPGAs.aspx http://en.wikipedia.org/wiki/Verilog Spartan-3 FPGA Starter Kit Board User Guide