ARQUITECTURA DE COMPUTADORAS II

INTERRUPCIONES EN LA IBM PC
POLLING (SONDEO)

Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II

INTERRUPCIONES EN LA IBM PC
INTERRUPCIONES

Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II

INTERRUPCIONES EN LA IBM PC
La IBM PC original uso el controlador de interrupciones 8259. Este permita que se pudieran generen hasta 8 seales de interrupcin ( numeradas de 0 a 7). Estas lneas de interrupcin son llamadas lneas de Interrupt Request ( requerimiento de interrupcin) o IRQs

Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II

INTERRUPCIONES EN LA IBM PC
A partir de la IBM AT se incluyen 2 controladores de interrupcin, donde el segundo controlador (ESCLAVO) est conectado en cascada a la lnea de interrupcin 2 del primer controlador ( MAESTRO) . L a lneas de interrupcin del segundo controlador estn numeradas de 8 a 15. Debido a este cascadeo, la lnea de interrupcin 2 no est disponible. Sin embargo ; para compatibilidad con la PC original, la lnea de interrrupcin 2 es conectada a al lnea 9 del segundo controlador ( tal que, si un dispositivo en la PC es configurado para la interrupcin 2, en realidad ste usa la interrupcin 9)

Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II

INTERRUPCIONES EN LA IBM PC
3FFF

Tenemos 1024 localidades de RAM en la parte ms baja de la memoria que permiten 256 vectores de interrupcin de 4 bytes cada uno.

Tabla de vectores de interrupcin

Vector 0

IPL IPH CSL CSh

0003

0002
0001 0000

TABLA DE VECTORES DE INTERRUPCIN

Un vector de interrupcin est formado por la direccin ( 2 bytes para CS y 2 bytes para IP) de inicio de la rutina de servicio de la interrupcin ISR esto es expresado como: CS:IP

Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II

INTERRUPCIONES EN LA IBM PC
Entradas del controlador programable de interrupciones PIC 8259

Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II

INTERRUPCIONES EN LA IBM PC
Registro de mscara de Interrupcin
The interrupt mask register is an eight bit register that lets you individually enable and disable interrupts from devices on the system. This is similar to the actions of the cli and sti instructions, but on a device by device basis. Writing a zero to the corresponding bit enables that devices interrupts. Writing a one disables interrupts from the affected device. Note that this is non-intuitive. Figure 17.1 provides the layout of the interrupt mask register.

Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II

INTERRUPCIONES EN LA IBM PC
When an interrupt occurs, regardless of source, the 80x86 does the following: 1) The CPU pushes the flags register onto the stack. 2) The CPU pushes a far return address (segment:offset) onto the stack, segment value first. 3) The CPU determines the cause of the interrupt (i.e., the interrupt number) and fetches the four byte interrupt vector from address 0:vector*4. 4) The CPU transfers control to the routine specified by the interrupt vector table entry. After the completion of these steps, the interrupt service routine takes control. When the interrupt service routine wants to return control, it must execute an iret (interrupt return) instruction. The interrupt return pops the far return address and the flags off the stack. Note that executing a far return is insufficient since that would leave the flags on the stack.

Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II

INTERRUPCIONES EN LA IBM PC
The PICs interface to the system through four I/O locations: ports 20h/0A0h and 21h/0A1h. The first address in each pair is the address of the master PIC (IRQ 0-7), the second address in each pair corresponds to the slave PIC (IRQ 8-15 ). Port 20h/0A0h is a read/write location to which you write PIC commands and read PIC status, we will refer to this as the command register or the status register. The command register is write only, the status register is read only. They just happen to share the same I/O location. The read/write lines on the PIC determine which register the CPU accesses. Port 21h/0A1h is a read/write location that contains the interrupt mask register, we will refer to this as the mask register. Choose the appropriate address depending upon which interrupt controller you want to use.

Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II

INTERRUPCIONES EN LA IBM PC
Int. Num. Address in I.V.T. Description

0 1 2 3 4 5 6

00-03 04-07 08-0B 0C-0F 10-13 14-17 18-1B

CPU divide by zero Debug single step Non Maskable Interrupt (NMI input on processor) Debug breakpoints Arithmetic overflow BIOS provided Print Screen routine Reserved

7
8 9 A B C
Carlos Canto Q.

1C-1F
20-23 24-27 28-2B 2C-2F 30-33

Reserved
IRQ0, Time of day hardware services IRQ1, Keyboard Interface IRQ2, ISA Bus cascade services for second 8259 IRQ3, Com 2 hardware IRQ4, Com1 hardware

ARQUITECTURA DE COMPUTADORAS II

INTERRUPCIONES EN LA IBM PC
D E F 10 11 12 13 14 34-37 38-3B 3C-3F 40-43 44-47 48-4B 4C-4F 50-53 IRQ5, LPT2, Parallel port hardware (Hard Disk on XT) IRQ6, Floppy Disk adaptor IRQ7, LPT1, Parallel port hardware Video services, see note 1 Equipment check Memory size determination Floppy I/O routines Serial port I/O routines

15
16 17 18 19 1A

54-57
58-5B 5C-5F 60-63 64-67 68-6B

PC used for Cassette tape services

Keyboard I/O routines Printer I/O routines Points to basic interpreter in a "real" IBM PC Bootstrap loader Time of day services

Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II

INTERRUPCIONES EN LA IBM PC
1B 1C 1D 1E 1F 20 21 22 23 24 25 6C-6F 70-73 74-77 78-7B 7C-7F 80-83 84-87 88-8B 8C-8B 90-93 94-97 Services Ctrl-Break service Timer tick (provides 18.2 ticks per second) Video parameters Disk parameters Video graphics Program termination (obsolete) All DOS services available through this Interrupt Terminate address Ctrl-Break exit address Critical error handler Read logical sectors

Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II

INTERRUPCIONES EN LA IBM PC
26 98-9B Write logical sectors

27
28 to 3F 40 to 4F 50 51 52 to 59 5A 5B 5D 5E 5F

9C-9F
A0-A3 to FC-FF 100-103 to 13C-13F 140-143 144-147 148-14B to 164-167 168-16B 16C-16F 174-177 178-17B 17C-17F

Terminate and stay resident routines (obsolete)

Reserved for DOS Reserved for BIOS Reserved for BIOS Mouse functions Reserved for BIOS Reserved for BIOS Reserved for BIOS Reserved for BIOS Reserved for BIOS Reserved for BIOS

60 to 66
67

180-183 to 198-19B
19C-19F

Reserved for User programs

Used for EMS functions

Carlos Canto Q.

ARQUITECTURA DE COMPUTADORAS II

INTERRUPCIONES EN LA IBM PC
68 to 6F 70 71 72 73 74 75 76 77 78 to 7F 1A0-1A3 to 1BC-1BF 1C0-1C3 1C4-1C7 1C8-1CB 1CC-1CF 1D0-1D3 1D4-1D7 1D8-1DB 1DC-1DF 1E0-1E3 to 1FC-1FF Unused IRQ8, ISA bus Real time clock IRQ9, takes the place of IRQ2 IRQ10 (available hardware interrupt) IRQ11 (available hardware interrupt) IRQ12 (available hardware interrupt) IRQ13, maths co-processor IRQ14, ISA bus hard disk controller IRQ15, (available hardware interrupt) Unused

80 to 85
86 to F0 F1 to FF

200-203 to 214-217
218-21B to 3C0-3C3 3C4-3C7 to 3C4-3FF

Reserved for basic

Used by basic Unused

Carlos Canto Q.