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Sam Siewert
Event Sensedd
Interrupt
Dispatch
Preemption
Dispatch
Input Latency
Dispatch Latency
Execution
Interference
Execution
Output Latency
Time
Sam Siewert
Services and IO
Initial Input IO from Sensors
Low-Rate Input: Byte or Word Input from Memory-Mapped Registers or IO Ports High-Rate Input: Block Input from DMA Channels and Block Reads from FIFOs
Intermediate IO
During Service Execution, Memory Mapped Register IO External Memory IO Cache Loads and Write-Backs In Memory Input/Output from Service to Service
Sam Siewert
Sensor Electronics
Sensors
Sam Siewert
Environment
Sam Siewert
Multi-Service Pipelines
frameRdy interrupt
RT Management
Control Plane
RGB32 buffer
tNet (2 Hz)
P0
P2
tCamCtl (3 Hz)
P3
SW HW
Bt878 PCI NTSC decoder (30 Hz) Serial A/B ISA ethernet
Sam Siewert
IF
ID
IF
ID
IF
ID
IF
ID
IF
ID
Execute
WriteBack
Sam Siewert
Service Execution
WCET (CPI bestcase Longest Path Inst Count) Stall Cycles Clk Period
Efficiency of Execution Memory Access for Inter-Service Communication Intermediate IO Ideally Lock Data and Code into Cache or Use Tightly Coupled Memory
Sam Siewert
Service Efficiency
Path Length for a Release
Instruction Count Longest Path Given Algorithm
Branches Loop Iterations Data Driven?
Path Execution
Number of Cycles to Complete Path Clocks Per Instruction Number of Stall Cycles for Pipeline
Data Dependencies (Intermediate IO) Cache Misses (Intermediate Memory Access) Branch Mis-predictions (Small Penalty)
Sam Siewert 9
Overlap
Di >= IOT is required; otherwise if Di < IOT, Si is IO-Bound Di >= ICT is required; otherwise if Di < ICT, Si is CPU-Bound Di >= (IOT + ICT) requires no overlap of IOT with ICT if Di < (IOT + ICT) where (Di >= IOT and Di >= ICT), overlap of IOT with ICT is required if Di < (IOT + ICT) where (Di < IOT or Di < ICT), deadline Di cant be met regardless of overlap
Sam Siewert 11
5700
5700 5300 4900 4500 4100 3700 3300 2900 2500 2100 1700 1300
4300
5000
2900
3600
500
Sam Siewert
100 100
900
800
1500
2200
13
S1
Msg
S2
Ptr
S2
Sam Siewert