Service System Integration and IO

ECEN 4623/5623 Lecture 6

November 19, 2003

Sam Siewert

Review of Service Response Timeline

Response Time = TimeActuation TimeSensed (From Event to Response)

Event Sensedd

Interrupt

Dispatch

Preemption

Dispatch

Completion (IO Queued)

Actuation (IO Completion)

Input Latency

Dispatch Latency

Execution

Interference

Execution

Output Latency

Time

Sam Siewert

Services and IO
Initial Input IO from Sensors
Low-Rate Input: Byte or Word Input from Memory-Mapped Registers or IO Ports High-Rate Input: Block Input from DMA Channels and Block Reads from FIFOs

Final Response IO to Actuators

Low-Rate Output: Byte or Word Writes Posted to Output FIFO or Bus Interface Queue High-Rate Output: Block Output on DMA Channels and Block Writes

Intermediate IO
During Service Execution, Memory Mapped Register IO External Memory IO Cache Loads and Write-Backs In Memory Input/Output from Service to Service

Sam Siewert

Service Integration Concepts

Initial Sensor Input and Final Actuator Response Output
Device Interface Drivers

Simple Service Has No Intermediate IO, No Synchronization

Sensor Input Interface Digital Control Law Service Actuator Output Interface

Sensor Electronics

Sensors

Actuator Electronics Effectors

Sam Siewert

Environment

Complex Multi-Service Systems

Multiple Services Synchronization Between Services Communication Between Services Multiple Sensor Input and Actuator Output Interfaces Intermediate IO, Shared Memory, Messaging

Sam Siewert

Multi-Service Pipelines
frameRdy interrupt

RT Management

Event releases / Service control frameRdy

Control Plane

RGB32 buffer

grayscale buffer frame

Data Plane Remote Display tFrmLnk (2 Hz)

tBtvid (30 Hz)

tFrmDisp (10 Hz)

tNet (2 Hz)

P0

tOpnav (15 Hz)

TCP/IP pkts tTlmLnk (5 Hz) P1

tThrustCtl (15 Hz)

P2

tCamCtl (3 Hz)

P3

SW HW
Bt878 PCI NTSC decoder (30 Hz) Serial A/B ISA ethernet

Sam Siewert

Pipelined Architecture Review

Recall that Pipeline Yields CPI of 1 or Less Instruction Completed Each CPU Clock Unless Pipeline Stalls!
IF ID Execute
WriteBack Execute WriteBack Execute WriteBack Execute WriteBack Execute WriteBack

IF

ID

IF

ID

IF

ID

IF

ID

IF

ID

Execute

WriteBack

Sam Siewert

Service Execution
WCET (CPI bestcase Longest Path Inst Count) Stall Cycles Clk Period

Efficiency of Execution Memory Access for Inter-Service Communication Intermediate IO Ideally Lock Data and Code into Cache or Use Tightly Coupled Memory

Sam Siewert

Service Efficiency
Path Length for a Release
Instruction Count Longest Path Given Algorithm
Branches Loop Iterations Data Driven?

Path Execution
Number of Cycles to Complete Path Clocks Per Instruction Number of Stall Cycles for Pipeline
Data Dependencies (Intermediate IO) Cache Misses (Intermediate Memory Access) Branch Mis-predictions (Small Penalty)
Sam Siewert 9

Hiding Intermediate IO Latency (Overlapping CPU and IO)

ICT = Instruction Count Time (Time to execute a block of instructions with no stalls = CPU Cycles x CPU Clock Period) IOT = Bus Interface IO Time (Bus IO Cycles x Bus Clock Period) OR = Overlap Required percentage of CPU cycles that must be concurrent with IO cycles NOA = Non-Overlap Allowable for Si to meet Di percentage of CPU cycles that can be in addition to IO cycle time without missing service deadline Di = Deadline for Service Si relative to release (interrupt initiating executon) CPI = Clocks Per Instruction for a block of instructions
Sam Siewert 10

Overlap
Di >= IOT is required; otherwise if Di < IOT, Si is IO-Bound Di >= ICT is required; otherwise if Di < ICT, Si is CPU-Bound Di >= (IOT + ICT) requires no overlap of IOT with ICT if Di < (IOT + ICT) where (Di >= IOT and Di >= ICT), overlap of IOT with ICT is required if Di < (IOT + ICT) where (Di < IOT or Di < ICT), deadline Di cant be met regardless of overlap
Sam Siewert 11

Service Execution Efficiency

CPIworst-case = (ICT + IOT) / ICT CPIbest-case = (max(ICT, IOT)) / ICT CPIrequired = Di / ICT OR = 1 - [(Di - IOT) / ICT] CPIrequired = [ICT(1-OR) + IOT] / ICT NOA = (Di IOT) / ICT OR + NOA = 1 (by definition)
Sam Siewert 12

Overlap Required for ICT and IOT Given Di=5000 nsecs

OR Function(ICT,IOT) for IOT and/or ICT > CT
1.7-1.8 1.6-1.7 1.5-1.6 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 Overlap Required (OR) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 1.4-1.5 1.3-1.4 1.2-1.3 1.1-1.2 1-1.1 0.9-1 0.8-0.9 0.7-0.8 0.6-0.7 0.5-0.6 0.4-0.5 0.3-0.4

5700

5700 5300 4900 4500 4100 3700 3300 2900 2500 2100 1700 1300

4300

5000

0.2-0.3 0.1-0.2 0-0.1 -0.1-0 -0.2--0.1

2900

3600

500

Sam Siewert

100 100

Instruction Count Time (ICT) nanosecs

900

800

1500

CPU Core IO Time (IOT) nanosecs

2200

13

Synchronization and Message Passing

Message Queues
Provide Communication Provide Synchronization
Msg

S1
Msg

S2

Traditional Message Queue

Message Size Internal Fragmentation
Heap Buffer Pool

Heap Message Queue

Messages Are Pointers Message Data in Heap
S1 Allocation Of Message Heap

Ptr

S2

Sam Siewert

De-Allocation Of Message Heap 14