Академический Документы
Профессиональный Документы
Культура Документы
Custom
Semicustom
Cell-based
Array-based
Macro Cells
FPGA's
Design Iteration
Tape-out
(> $2M just for the mask costs) Very high re-spin cost
FPGAs
FPGA: Field-Programmable Gate Array
Circuit Description
Gate Array
logic
- lookup tables and flip-flops Altera: LABs Xilinx: CLBs
I/O Blocks - interface off-chip - can usually support many I/O Standards
Logic Block Connection Block Switch Block Routing Track (Horizontal) Routing Channel (Vertical)
TILE
Logic Block:
Basic Logic Gate: Lookup-Table
Inputs
Bit-Stream Function of each lookup table can be configured by shifting in bit-stream.
Logic Clusters
Local Interconnect
D Q
Several lookup tables are grouped into clusters - Typically 8 to 10 lookup tables per cluster Connections between lookup tables in the same cluster are fast Connections between lookup tables in different clusters are slow
D Q
D Q
Logic Block Connection Block Switch Block Routing Track (Horizontal) Routing Channel (Vertical)
Reconfigurable Logic:
Connect Logic Blocks using Fixed Metal Tracks and Programmable Switches
Reconfigurable Logic:
Connect Logic Blocks using Fixed Metal Tracks and Programmable Switches
Hardwired multipliers
High-speed I/O
Advantages of FPGAs:
"Instant Manufacturability": reduces time to market Cheaper for small volumes because you dont need to pay for fabrication
means you dont need to be a big company to make a chip
Disadvantages of FPGAs:
Slower than custom or standard cell based chips Cannot get as much circuitry on a single chip Today: ~ 1M gates is the best you can do ~ 200 MHz is about as fast as you can get
For large volumes, it can be more expensive than gate arrays and custom chips
Structured ASICs
Combines good features of FPGAs and Standard Cell ASICs
- Structured ASIC
Some layers are generalized while a few layers are customized for a circuit
Transistors
- FPGA
All the layers are generalized for any circuit
Logic Blocks
Choices
Fine Grained
Basic gates: NAND, NOR, XOR, FF etc.
Medium Grained
Lookup Tables
Coarse Grained
Multi-input, Multi-output blocks (e.g., PLAs)
Configurability
SRAM cells Vias
Lower Level (e.g., between M1 and M2) Upper Level (Via stacks brought up to the configurable layers)
Routing Fabrics
Metal and Via Programmable
More flexibility, more efficiency Employed in most structured ASIC offerings
Via Programmable
Regular, easy to manufacture Metal is fixed and every segment may not be fully utilizable,
Can be Inefficient
Design Flows
Design Flows
Design Flows
Design Flows
Design Flows
Design Iteration
Tape-out