PROGRAMMABLE LOGIC CONTROLLER

MELSEC-AnS, QnAS

Compact size controller

Q2AS(H) (Vertual I/O)

Q2AS(H)-S1 A2S-S1

A2AS-S (Vertual I/O) A2AS-S1,S30,S60,M128

Control I/O size

Q2AS(H) (Vertual I/O) A2AS (Vertual I/O)

Q2AS(H) A2AS A2S

A1S-S1

A1S

A1SJ

8192

1024

512

256

Program execution speed

1us

A1S-S1

A2S-S1

A1SJ

A2S

A1S

0.2us 0.15us 0.075us

A2AS-S30 A2AS-S1

Q2AS-S1

A2AS-S60,M128

Processing speed of 1 contact/coil command

Q2AS A2AS

Q2ASH-S1

Q2ASH

MELSEC-QnA/QnAS

Innovation of programming

Concept
Structured

programming Program standardization Simplification of program

Structured program management

Up

to 124 of parameter, program, comment and device data files can be created and loaded into the CPUs built-in memory and/or IC card memories. Capability to handle multiple program files makes each program smaller so that maintenance and debugging of the programs can be easier.

Structured program management

Programs divided based on designer
Designer A Designer B Designer C

QnA CPU Program A Program B Program C

Programs divided based on process

Feed-in process Assembly process Feed-out process

QnA CPU Program A Program B Program C

Structured program management

Simultaneous

debugging

Program A

Program B

While a designer is debugging Program A via the CPU front port, another designer can debug Program B via AJ71QC24.

Attribution of program
Initial

program
Programs only once after power-on

Scanning Low

program

Programs executed repeatedly

speed program
Programs executed in the constant scan loop

Waiting

program

Programs executed when initiated by interrupts or subroutine calls

Attribution of program
Initial programs Scanning programs
Power-on System initialization Sp. initial Cutting Assemble Paint

Low speed programs

Monitor Logging Diagnostic

Waiting programs
Error routine Scheduler

Structured program management

Global

device & Local device

Program B B0 X100 M100
M0 M0

Program A X0 X0 X1 X2
M100

X1 X2

Because M0 is a local device, M0 in Program A and M0 in Program B can operate independently. Because M100 is a global device, status of M100 in Program A is relayed to M100 in Program B. Note: Range of each device type as local device can be defined by the user

Structured program management

Global

device & Local device

M V T ST C D

Local devices can be assigned in the following

devices

Internal relay Edge relay Timer Retentive timer Counter Data register

Program standardization
Macro

command

A program block often used in a program can

be registered as a user-defined macro command

Program standardization
Subroutine

call with arguments

A subroutine program can be called from

another program with input arguments and output arguments, similar to function call of C language.

Program standardization
Subroutine
Main routine program X0 [CALL P0 M1 M2 D0 ] P0 FX0 FX0 M0

call with arguments

Sub routine [MOV FD1 R0 ] FY1 [RET ]

Up to 5 arguments can be used

Simplification of program
Programming
When program
Start Ready Stop
Ready

with labels
Label definition
Label Device Comment [Start] [X0 [System ] start ] [Stop] [X1 [Cycle ] stop ] [Ready] [Y10 [Operation ] ready ]

Converter to program
X0 Y10 X1
Y10

Simplification of program
New

data devices
X0 D0.0

Bit specification of a register device

D0.A

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Simplification of program
New
X0

data devices
DX10 DY100
Output is made when the command is executed. Input is made when the command is executed. Input is made in the end of scan.

Direct access input and output

Simplification of program
New

data devices
X0 X1 Y100 Y100
X0 contact in the program only close for one scan after X0 changes its status from OFF to ON. In the conventional program, PLS command has to used to make a equivalent program.

Differential contact

Simplification of program
New

data devices
[MOV U5\G12 D0 ]

Direct addressing of special function module

X0

U5: Signifies a special module located on address X/Y50 G12: Signifies address 12 of the special module In a conventional program, FROM/TO command has to be used instead.

Simplification of program
New

data devices

Character strings
X0 [$+P D5 -S1 R10 ] D5 - D8 R10 - R14 + -S1

Q2ACPU

Q2ACPU-S1

Simplification of program
Device

initial data

QnA can hold a device initial data file where

initial setting data of devices are registered, and transfers this data into device memory when the CPU is set to RUN. This feature eliminates programs which set initial data in the devices and the buffer memory of special modules

Simplification of program
Device

initial data
Device initial data file
[MOV H100 D0 ] [MOV H200 D1 ]

Initialization program (Conventional method)

[TO H2 K100 H100 K1 ]

Device memory T, ST, C, D, W

Sp. module buffer memory

Hardware Features
High

speed processing
A4UCPU 0.15 s 0.90 s Q4ACPU 0.075 s 0.225 s

Contact/ Coil MOV

On average, Q4ACPU is approx.. 3 times faster than A3A/A3U/A4UCPU.

Hardware Features
Program

memory

Max. program size :124 kstep (Series execution) Efficient memory management :1.7 times better

File

memory

Compatible with IC memory card Max. 2MB x 2 memory size

QnA Series CPU modules

Q4ACPU : 4096 I/O, 124kstep, 0.075us/step Q3ACPU : 2048 I/O, 92kstep, 0.15us/step Q2ACPU-S1: 1024 I/O, 60kstep, 0.15us/step Q2ACPU : 512I/O, 28kstep, 0.2us/step

Network modules
AJ71QLP21, AJ71QLP21S : MELSECNET/10 AJ72QLP25 : MELSECNET/10 AJ71QBR11 : MELSECNET/10 AJ72QBR15 : MELSECNET/10 AJ71QC24/R2/R4 :RS232C/485

QnAS Series CPU modules

Q2ASHCPU-S1: 1024 I/O, 60kstep, 0.075us/step Q2ASHCPU : 512 I/O, 28kstep, 0.075us/step Q2ASCPU-S1 : 1024 I/O, 60kstep, 0.2us/step Q2ASCPU : 512I/O, 28kstep, 0.2us/step

Q4ARCPU System

A Hot/Stand-by system
Mitsubishi Electric Corporation

Q4ARCPU System

Q4ARCPU System
Single

system: Utilize Q4ARs extended calculation ability Dual system: Configuration of a hot/stand-by system and/or utilize Q4ARs extended calculation ability

 Single

system configuration

Q4ARCPU

 Single

system configuration

Q4ARCPU

Power supply

P R16 A

A38HB base rack required

 Single

system configuration

Q4ARCPU

CPU

P R16 A

RA4 Q

A38HB base rack required

 Single

system configuration

Q4ARCPU

P R16 A

I/O modules
A38HB base rack required

RA4 Q

 Single

system configuration w/dual power

Q4ARCPU

supply

 Single

system configuration w/dual power

Q4ARCPU

supply

Power supply

P R16 A P R16 A

Power supply
A37RHB base rack required

 Single

system configuration w/dual power

Q4ARCPU

supply

P R16 A P R16 A

CPU

RA4 Q

A37RHB base rack required

 Single

system configuration w/dual power

Q4ARCPU

supply

P R16 A P R16 A

I/O modules
A37RHB base rack required

RA4 Q

 Dual

system configuration

Q4ARCPU

 Dual

system configuration

Q4ARCPU

Power supply

P R16 A

P R16 A

Power supply

A33RB base rack required

 Dual

system configuration

Q4ARCPU

P R16 A

CPU

CPU

A33RB base rack required

P R16 A

RA4 Q

RA4 Q

 Dual

system configuration

Q4ARCPU

R29S A RA4 Q F AR6 A

System BUS I/F monitor

RA4 Q R29S A

System monitor

A33RB base rack required

 Dual

system configuration

Q4ARCPU

11 RB Q R29S A RA4 Q F AR6 A

RA4 Q R29S A 11 RB Q

P R16 A

P R16 A

MELSECNET/10

Network

Network

A33RB base rack required

 Dual

system configuration

Q4ARCPU

F AR6 A

RA4 Q R29S A 11 RB Q 11 RB Q P R16 A Network

P R16 A 11 RB Q 11 RB Q R29S A RA4 Q

MELSECNET/10 MELSECNET/10

Network

A33RB base rack required

 Dual

system configuration

Q4ARCPU

P R16 A 11 RB Q 11 RB Q R29S A RA4 Q F AR6 A

RA4 Q R29S A 11 RB Q 11 RB Q P R16 A

MELSECNET/10 MELSECNET/10

P R16 A P R16 A

Extension Rack

A33RB base rack required

 Dual

system configuration

Q4ARCPU

P R16 A 11 RB Q 11 RB Q R29S A

RA4 Q R29S A 11 RB Q 11 RB Q P R16 A

RA4 Q F AR6 A

MELSECNET/10 MELSECNET/10

P R16 A P R16 A

I/O modules
A33RB base rack required

Configuration
Over

all system
A NQ

MELSECNET/10 PLC net

MELSECNET/10 remote I/O net, or PLC net

Specifications: Q4ARCPU
Processing

speed of sequence command: 0.075us/step. Max. No. of input/output points: 4096 points With remote I/O system; up to 8192 I/O control Program capacity: 124K steps

Specifications: Q4ARCPU
Multiple

program capacility; up to 124 Up to 4MB memory capacity (IC memory card required)

Data Tracking
Data

necessary for back-up are copied every scan to the stand-by CPU via the data tracking bus so that seamless control at hotstand-by switching time is realized.
Up to 48kW data tracking per scan

On-line

program tracking

Program change to the active CPU is copied to

the stand-by CPU

Duplicated Network
This

system is fully compatible to the MELSECNET/10 high speed duplicated network system. MELSECNET/10 redundancy
By cable disconnection By network module failure

Extended self-diagnostic functions

Power

supply 5VDC voltage drop Power supply 24VDC voltage drop Power supply failure detection CPU self-diagnostics AS92Rs CPU healthy check

New process commands

S.IN S.OUT1 S.PID S.PHPL S.LLAG S.I S.D S.DED S.FG S.IFG S.FLT S.ENG S.IENG S.ABS Analog input Output with mode switching Basic PID Upper/lower limit alarm Leading lag Integration Derivative Dead time Function generation Function reverse generation Filter Engineering value conversion Engineering value reverse conversion Absolute

Math co-processor
For

high speed floating point math calculation

Command + SI N COS TAN A3ACPU 476 us 482 us 228 us 746 us 4620 us 4920 us 4970 us Q4ACPU 238 us 241 us 114 us 373 us 2310 us 2460 us 2485 us Q4ARCPU 35 us 35 us 35 us 38 us 34 us 34 us 37 us

System switching
The

bus switching module A6RAF switch the I/O bus from the hot CPU to the standby CPU when the system control module detects either of:
CPU's self-diagnostic error (reported by the CPU itself), or the CPU stops to reset the WDT in the system control module. MELSECNET error detected

Module Specifications
AS92R:

System control module

CPU operations are monitored. Monitor of power supply modules +5V output. CPU health check with WDT counter.

A61RP:

Power supply module

Duplicated power supply unit. Performance equivalent to A61P. DC5V output drop detection function..

Module Specifications
A6RAF:

Bus switch module

Control changeover function. Control mode changeover.

A32RB,

A33RB: Redundancy CPU base

Basic base for duplicated CPU system configuration (2 or 3 I/O slots each for each side)

Module Specifications
A37RHB:

PS redundancy base

A37RHB for single CPU system with duplicated power supply modules (7 I/O slots)

A68RB:

Extension base

8 I/O slots with duplicated power supply modules

The connection of the I/O bus to a CPU can be

switched manually by the switch located on the bus switching module.

Redundancy By MELSECNET-10

Mitsubishi Electric Corporation

A1S32B

MNET-10 Q2ASCPU A1S61PN A1SY41 A1SX41-S2 MNET-10 A1SX41-S2 MNET-10 A1S32B A1S61PN

System Configuration

Q2ASCPU A1S61PN

A1S38B

REDUNDANT MELSECNET/10

NP16 S1 A DA86 S1 A DA86 S1 A I A D86 S1 A 2S - 14 XS1 A 2S - 14 XS1 A 2S - 14 XS1 A DA86 S1 A DA86 S1 A 2R - 42 C Q 17J S1 A REDUNDANT SCADA CONNECTIVITY DA86 S1 A NP16 S1 A UP CSA2 Q 12 PL Q 17J S1 A 2 S2 R42 CU17J S1 A DA86 S1 A DA86 S1 A DA86 S1 A 52 PL Q 27J S1 A UP CSA2 Q 12 PL Q 17J S1 A

NP16 S1 A

NP16 S1 A

System Configuration

DA86 S1 A 2 S2 R42 CU17J S1 A

REDUNDANT MODBUS CONNECTIVITY

SCADA Printer

B N70 CS1 A P16 A NP16 S1 A 01 - TEN M 4 / 3 DR86 A 4 / 3 DR86 A DA616 A NP16 S1 A

B70 CS1 A

B70 CS1 A NP16 S1 A UP CSA2 Q 01 - TEN M

I/Os

I/Os

DA616 A DA616 A

I/Os
NP16 S1 A

kn iL - CC A1S68B 42 C Q 17J S1 A A1S38B

A1S58B

UP CSA2 Q 01 - TEN M

A68B Remote I/O modules AJ65-SBTB1-32D, DI modules. AJ65-SBTB1-32T, DO modules.

System configuration

... ...

SCADA / Application software

Printer

System configuration

A1SJ71QC24-R4 A1SY42 A1SY42 A1SY42 A1SY42 A1SX42 A1SX42 ETHERNET A1SJ71QC24-R4 A1SJ71QLP21 Q2ASCPU A1S61P A1SX42 A1SX42 A1SJ72QLP25 A1S61P A1SJ71QLP21 Q2ASCPU A1S61P

System configuration

A1SJ71C24-R4S2 A1SJ61QBT11 Q2ASCPU A1S61P

ETHERNET

A1SJ71C24-R4S2 A1SJ61QBT11 Q2ASCPU A1S61P

Questions ?

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