RFIC Design Issues

Suchitav Khadanga
RFIC Technologies
www.rficdesign.com
 RFIC Design Flow
 System Level Specification
 System Analysis and Architecture Choice
 Chip Set Partitioning and Chip Level
Specification
 Preliminary RFIC Design topology Trade off
 Detailed Design Phase
 RFIC Layout
 Parasitic Extraction and Re simulation
 Fabrication
 Evaluation to Specification
RFIC Technologies, www.rficdesign.com
 System Level Specification
 System Level Specification
 Each next day brings challenging specification
 Individual module works fine,
 Integration of the full system partially functioning
 How to make simulation faster
 Alternative methods to find error earlier
 Where are the impedances to take care and
where to neglect
 Which issues we will visit in next version of
chip
RFIC Technologies, www.rficdesign.com
 Transreceiver Architecture
 Super heterodyne, Direct Conversion, Zero IF,
Low IF Receiver architecture ?
 Which is the best
 Which transmitter
 What is the role of frequency synthesizer
 Separate chip for Power Amplifier ?
 LNA switch and power amplifier in a separate
chip
 What is component count , size in real use ?
RFIC Technologies, www.rficdesign.com
 Phase Noise of Synthesizer
 Depends primarily on the VCO
 How to reduce flicker noise of VCO
 VCO Phase noise suffers from the Low Q
of on chip inductors
 Off chip passives can be used to improve
the phase noise performance, but cost
more
 Is the frequency range in the linear
 How to calibrate the frequency of VCO
RFIC Technologies, www.rficdesign.com
 Low Noise Amplifier
 Number of inductors required for the LNA
 Inductor less LNA
 How to make a good combination between
switch on one side, and mixer on the other side
 Should we put LNA switch and PA as a separate
chip
 Can we achieve less than 0.5dB noise figure in
CMOS , yes!

RFIC Technologies, www.rficdesign.com
Choice of Process Technology
 CMOS the best one, we like
 What is best for the application 45nm or
180nm
 Bi-CMOS seems good , if there is issue
with CMOS technologies, costs more
 SiGe, leader for power amplifier
parameters
 GaAs , Still not good for both cost and
performance
 or any other RFIC Technologies, www.rficdesign.com
 Analog LAYOUT
 Proper isolation
 Guided wave terminology
 Make a metal box, as aluminum box in RF PCB
design
 Impedance Mismatch
 Metal Lines are Transmission Lines
 Where will I put my digital blocks, pads
 How many grounds needed for the chip.

RFIC Technologies, www.rficdesign.com

 Challenges
 Taking care of on chip parasitics
 Providing separate grounding for RF Analog and
digital portions to avoid noise and crosstalk
problems
 Integration of RF and Digital leads to EMI/EMC
problems

RFIC Technologies, www.rficdesign.com

 Thanks
 We are here for answering all the problems
 Drop a mail to ceo@rficdesign.com , we will be
pleased to have communication with you
 We are experts in wireless, analog development
systems, circuits, layouts…
 Our main office is in bangalore, India

RFIC Technologies, www.rficdesign.com