Radix-2 Encoding

Algorithm inefficient with isolated 1's Example: 001010101(0) recoded as 011111111 , requiring 8 instead of 4 operations Situation can be improved by examining 3 bits of X at a time rather than 2

Radix-4 Encoding

Modified Booths Encoder

y(2i+1) y(2i) y(2i-1) y(i)` X 2X Sign Zero

0 0 0

0 0 1

0 1 0

0 1 1

0 1 1

0 0 0

0 0 0

1 0 0

0
1 1 1 1

1
0 0 1 1

1
0 1 0 1

2
-2 -1 -1 1

0
0 1 1 0

1
1 0 0 0

0
1 1 1 1

0
0 0 0 1

Simplified sign extension method

PP83

1 PP82 PP83 PP73

1 PP82 PP63

PP80 PP81 PP72 PP53

PP80 PP81 PP62 PP43

PP80 PP71 PP52 PP33

PP80 PP61 PP42 PP23

PP70 PP51 PP32 PP13

PP60 PP50 PP40 PP30 PP20 PP10 PP00 PP41 PP31 PP21 PP11 PP01 S PP22 PP12 PP02 S PP03 S S
P6 P5 P4 P3 P2 P1 P0

P15

P14

P13

P12

P11

P10

P9

P8

P7

Proposed Modified Booths Encoder

Proposed Booth selector

Adding Last Row of PP with Sign bit: We add last PP row with corresponding sign bit. It is done to avoid usage of higher level of compressor. Only 10 bit Half adders are used instead of Full adders if compressors were used.

Compression of PP using 4:2 Compressor

A 16-bit Parallel Adder to compute final sum (product): Done to compute the Sum of Sum and carry of compressor output.

Parallel addition is used Since it gives a reasonable speed with lesser area.

Logic gates used in Encoder and selctor

Logic gates used in No. of Logic gates used

Encoder and selector in Encoder and selector NOT 2 I/P -XOR 2 I/P-NAND 3 I/P-NAND 3 2 3 4

Result Analysis
Transistors used in our Proposed Design
Total Number of %Improvement/Enhancem

transistors in Encoder and

selector combined design (For comuting 1 PP)

ent in Number of
transistors with respect to Proposed design for Encoder and selector

Conventional Booth
multiplier[1] Modified Wen-Changs method[2]

62

-11%

90

+22%

Our Proposed Encoder and

Selector Z. Hung and M. D. Ercegovac Encoder and

70

66

-6%

Selector[5]

Speed Improvization
Propoagation Delay for Encoder and selector combined (Normalized %Improvement/Enhance ment in Propogation Delay with respect to

with respect to Inverter

i.e. Inverter delay is 1)

Proposed design for

Encoder and selector

Conventional Booth multiplier[1] Modified Wen-Changs method[2] Our Proposed Encoder

13.6

+45%

8.4

+12%

7.4

and Selector
Z. Hung and M. D. Ercegovac Encoder and 9.0 +17%

CONCLUSION
An efficient Booths Encoder and Selector has been developed using a redisigned MBE. With achieving 7.4 Normalized gate delay of propagation for Encoder and Selector, remarkable is the speed improvement. However the increase in sizing can be tolerated since the achieved speed is remarkable.

REFERENCES
[1] Neil Weste, David Harris (2005). CMOS VLSI DESIGN (3rd Ed). Pearson Publications. [2] Razaidi Hussein , Ali Yeon Md. Shakaff, Norina Idris, Zaliman Sauli, Rizalafande Che Ismail and Afzan Kamarudin. An Efficient Modified Booth Multiplier Architecture 2008 IEEE International Conference on Electronic Design. December 1-3, 2008, Penang, Malaysia. [3] Shiann-Rong Kuang, Jiun-Ping Wang, and Cang-Yuan Guo. Modified Booth Multipliers With a Regular Partial Product Array. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 56, NO. 5, MAY 2009. [4] Wen-Chang, Y. & Chein-Wei, J. High-speed Booth encoded parallel multiplier design, IEEE Transactions on Computer, 2000. [5] Z. Huang and M. D. Ercegovac, High-performance low-power left-to right array multiplier design, IEEE Trans. Comput., vol. 54, no. 3, pp. 272283, Mar. 2005.

REFERENCES
[6] Ercegovac. T. L. M. D. (2003). Digital Arithmetic. California, USA: Morgan Kaufmann Publishers.

[7] Razaidi et al, Analysis of various Modified Booth Encoder (MBE) and proposal for an efficient Modified Booth Encoder, IEEE Regional Symposium on Microelectronics, December, 2007 [8] Rizalafande Che Ismail, A Complex Multiplier Using Booth Wallace Algorithm, M.Eng. RMIT, 2005