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Half-Adder
This circuit needs 2 binary inputs and 2 binary outputs. The input variables designate the augend and addend bits:the output variables produce the sum and carry. Inputs Carry Sum X Y C S 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0
Full-Adder
Is a combinational circuit that forms the arithmetic sum of 3 bits. Consists of 3 inputs and 2 outputs. When all input bits are 0 , the output is 0. The output S equal to 1 when only one input is equal to 1 or when all 3 inputs are equal to 1. The C output has a carry of 1 if 2 or 3 inputs are equal to 1.
C=XY+XZ+YZ
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11
Z
C
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Implementation of Full Adder using only NAND gates (1)Boolean expressions in NAND form
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Implementation of Full Adder using only NAND gates (2) - Logic Diagram
C
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Implementation of Full Adder using only NOR gates (1)Boolean expressions in NOR form
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HALF SUBTRACTORS
Difference
00 01 10 11 = = = = 0 1 1 0
Borrow
0 1 0 0
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The truth table and the logic symbol for half subtractor
AB AB
AB
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The difference (Di) output column of the truth table is an XOR operation. Di = A B The Boolean expression for the borrow (B0) output is
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ABBin ABBin
ABBin
ABBin
ABBin
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Di = A B Bin
The borrow output of the FS can be derived by the truth table as follows.
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Di = A B Bin
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Di = A B Bin
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PARALLEL ADDER
Parallel Adder is a digital circuit that produces the arithmetic sum of 2 binary numbers. Constructed with full adders connected in cascade, with output carry from each full adder connected to the input carry of next full adder in the chain. The augend bits of A and the addend bits of B are designated by subscript numbers from right to left, with subscript 1 denoting the least significant bit. The carries are connected in a chain through the full adders.
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C0 2 1
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2-BIT PARALLEL ADDER USING A HALF ADDER AND A FULL ADDER (2)
A2A1 + B2B1 C0 2 1
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A2A1 + B2B1 C0 2 1
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Input carry
Augend
0
1
1
0
1
1
0
1
Cin
Ai
Addend
Sum Output carry
0
1 0
0
1 0
1
1 1
1
0 1
Bi
i C0
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The 4 bit parallel adders can be used to form 8 bit, 12 bit, 16 bit and 32 bit parallel adders.
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C2
C1
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1
478 +137 0100 0001
1
0111 0011 1000 0111
A decimal adder requires a minimum of nine inputs and five outputs, since four bits are required to code each decimal digit and the circuit must have an input and output carry. Consider the arithmetic addition of two decimal digits in standard BCD code (8421 code), together with an input carry from a previous stage.
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Since each input digit does not exceed 9, the output sum cannot be greater than 9+9+1 =19, the 1 in the sum being an input carry. Apply 2 BCD digits to a 4-bit binary adder. The adder will form the sum in binary and produce a result that ranges from 0 through 19. These binary numbers are listed in the table and are labeled by K, Z8,Z4,Z2,Z1 and K is carry. The columns under the binary sum list the binary value that appears in the outputs of the 4-bit binary adder
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K Z8
Z4
Z2
Z1
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0 0
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Decimal adder for Standard BCD Code (4) -Boolean function for correction
From the table, when the binary sum is equal to or less than 1001, the corresponding BCD number is identical, and therefore no conversion is needed. When the binary sum is greater than 1001, non valid BCD representation is obtained. Addition of binary 6 (0110) to the binary sum converts it to the correct BCD representation and also produces an output carry as required
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Decimal adder for Standard BCD Code (5) Boolean function for correction
A correction is needed when the binary sum has an output carry K=1. The other six combinations from 1010 through 1111 that need a correction have a 1 in position Z8. To distinguish them from binary 1000 and 1001, which also have a 1 in position Z8, it can be concluded that Z 4 or Z2 must have a 1. Therefore, the condition for a correction and an output carry can be expressed by the Boolean function:
C=K+Z8 Z 4+Z8 Z2
When C =1, it is necessary to add 0110 to the binary sum and provide an output carry for the next stage.
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Decimal adder for Standard BCD Code (6) Block Diagram of a BCD Adder
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