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Chapter 1.

Basic Structure of Computers

INTRODUCTION
This chapter discusses the computer hardware, software and their interconnection, and it also discusses concepts like Computer types Functional Units Bus Structures Performance Multiprocessor, RISC and CISC systems.
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COMPUTER TYPES
Computers are classified based on the parameters like

Speed of operation
Cost Computational power Type of application

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DESK TOP COMPUTER


Eg: Personal computers which is used in homes and offices Advantage: Cost effective, easy to operate, suitable for general purpose educational or business application

NOTEBOOK COMPUTER
Compact form of personal computer (laptop) Advantage is portability

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WORK STATIONS
More computational power
Costlier Used to solve complex problems which arises in engineering application (graphics, CAD/CAM etc)

ENTERPRISE SYSTEM (MAINFRAME)


More computational power

Larger storage capacity


Used for business data processing in large organization Commonly referred as servers or super computers

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SERVER SYSTEM
Supports large volumes of data which frequently need to be accessed or to be modified Supports request response operation

SUPER COMPUTERS
Faster than mainframes

Helps in calculating large scale numerical and algorithm calculation in short span of time
Used for aircraft design and testing, military application and weather forecasting

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Functional Units

Functional Units
Input
Memory Output Control Arithmetic and logic

I/O

Processor

Figure 1.1. Basic functional units of a computer.

Information Handled by a Computer


Instructions/machine instructions
Govern the transfer of information within a computer as well as between the computer and its I/O devices Specify the arithmetic and logic operations to be performed List of instructions is called a Program

Data
Used as operands by the instructions

INPUT UNIT:
Converts the external world data to a binary format, which can be understand by CPU Eg: Keyboard, Mouse, Joystick etc

OUTPUT UNIT:
Converts the binary format data to a format that a common man can understand Eg: Monitor, Printer, LCD, LED etc

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Memory Unit
Store programs and data Two classes of storage
Primary storage
Fast Programs must be stored in memory while they are being executed Large number of semiconductor storage cells Processed in words Distinct Address associated with each location

Secondary storage larger and cheaper

Arithmetic and Logic Unit (ALU)


Most computer operations are executed in ALU of the processor. Load the operands into memory bring them to the processor and store them in registers perform operation in ALU store the result back to memory or retain in the processor.

Control Unit
All computer operations are controlled by the control unit. The timing signals that govern the I/O or data or any transfers are also generated by the control unit.

Operations of a computer:
Accept information in the form of programs and data through an input unit and store it in the memory
Fetch the information stored in the memory, under program control, into an ALU, where the information is processed Output the processed information through an output unit Control all activities inside the machine through a control unit

Basic Operational Concepts

Review
Activity in a computer is governed by instructions. To perform a task, an appropriate program consisting of a list of instructions is stored in the memory. Individual instructions are brought from the memory into the processor, which executes the specified operations. Data to be used as operands are also stored in the memory.

A Typical Instruction
Add LOCA, R0 Add the operand at memory location LOCA to the operand in a register R0 in the processor. Place the sum into register R0. The original contents of LOCA are preserved. The original contents of R0 is overwritten. Instruction is fetched from the memory into the processor the operand at LOCA is fetched and added to the contents of R0 the resulting sum is stored in register R0.

Prev example combines a memory access operation with an ALU operation This can be realized as Load LOCA,R1 Add R1,R0 Transfers b/w the memory and the cpu are started by sending the address of the location to memory unit and issuing the appropriate control signals

MAR

MDR Control

PC

R0 R1 Processor

Connection Between the Processor and the Memory


IR ALU Rn 1

n general purpose registers

Figure 1.2. Connections between the processor and the memory.

Registers
Instruction register (IR)
instruction register holds the instruction that is currently being executed. Instruction present in IR will be decoded by which processor understand what operation it has to perform

Program counter (PC)


program counter keeps track of execution of program. Increments the contents of PC by 1, so that it points to the next instruction address

General-purpose register (R0 Rn-1) Memory address register (MAR) holds the address of the location to be accessed. Memory data register (MDR) contains the data to be written into or read out of the addressed location.

Typical Operating Steps


Programs reside in the memory through input devices PC is set to point to the first instruction The contents of PC are transferred to MAR A Read signal is sent to the memory The first instruction is read out and loaded into MDR The contents of MDR are transferred to IR The instruction is ready to be decoded and executed

Typical Operating Steps (Cont)


If the instruction involves an operation be performed by ALU, then Get operands
General-purpose register Memory (address to MAR Read MDR to ALU)

Perform operation in ALU Store the result back


To general-purpose register To memory (address to MAR, result to MDR Write)

During the execution of current instruction , PC is incremented to the next instruction

Interrupt
Execution may preempted if some device needs urgent servicing. Device raises an interrupt signal. Interrupt: request from an I/O device for service by the processor. Processor provides requested service by executing an appropriate interrupt service routine. Before servicing the interrupt the contents of PC, generalpurpose registers, and some control information are saved in memory After completion of interrupt service routine, state of the processor is restored and interrupted program may continue.

Bus Structures
There are many ways to connect different parts inside a computer together. A group of lines that serves as a connecting path for several devices is called a bus. Address/data/control

Input

Output

Memory

Processor

Bus Structure

Figure 1.3.

Single-bus structure.

Single-bus

Single-bus
Simplest way of interconnecting functional units All units are connected to this bus Can be used for only one transfer at a time, thereby only 2 units can actively use the bus at a time Low Cost and flexibility for attaching peripheral devices

Multiple Buses
To improve performance multibus structure can be used In two bus structure : One bus can be used to fetch instruction other can be used to fetch data, required for execution. Thus improving the performance

Also buffer registers can be used with the devices to hold the information during transfers smoothes out the timing difference between the cpu,memory and i/o devices

Performance

Performance
The most important measure of a computer is how quickly it can execute programs. Three factors affect performance:
Hardware design Instruction set Compiler

Performance
Processor time to execute a program depends on the hardware involved in the execution of individual machine instructions.

Main memory

Cache memory

Processor

Bus

Figure 1.5. The processor cache.

Processor Clock
Processor circuits are controlled by a timing signal clock Clock defines regular time intervals clock cycles Each instruction is divided into several basic steps, each of which completes in one clock cycle.

P length of one clock cycle is an important parameter that affects processor performance. The inverse of P is the clock rate R = 1/P which is measured in cycles per second (frequency or clock frequency) Clock rates ranges from few hundred million to over a billion cycles per second The term cycles per second used to measrue clock rate is termed as Hertz (Hz). MillionMega(M), billion Giga (G) 500 million/second500 MHz 1250 million per second is 1.25 GHs

Basic Performance Equation


T processor time required to execute a program that has been prepared in high-level language N number of actual machine language instructions needed to complete the execution (note: loop) S average number of basic steps needed to execute one machine instruction. Each step completes in one clock cycle R clock rate

N S T R
The execution time T has to be minimized for better performance. For which values of N and S must be minimized and value of R must be enhanced at the same time.

Clock Rate
Increase clock rate
Improve the integrated-circuit (IC) technology to make the circuits faster

Reduce the amount of processing done in one basic step.This will reduce clock period P and enhances R the clock rate.

Performance Measurement
Measure computer performance using benchmark programs. System Performance Evaluation Corporation (SPEC) selects and publishes representative application programs for different application domains, together with test results for many commercially available computers. A benchmark program from a suite of benchmark program will be selected and compiled for test computer. The same benchmark program will be compiled and executed on one of the typical computer which be selected as a Reference Computer SPEC95- reference comp- sun sparc station SPEC2000- reference comp- Ultra sparc10 workstation with a 300MHz UltraSparc Processor

Performance Measurement

Running time on a Reference Computer SPEC Rating = Running time on a test Computer

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EVOLUTION OF COMPUTERS
FIRST GENERATION (1945 1955)
Program and data reside in the same memory (stored program concepts John von Neumann) ALP was made used to write programs

Vacuum tubes were used to implement the functions (ALU & CU design)
Magnetic core and magnetic tape storage devices are used

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SECOND GENERATION (1955 1965)


Transistor were used to design ALU & CU

HLL is used (FORTRAN)


To convert HLL to MLL compiler were used Separate I/O processor were developed to operate in parallel with CPU, thus improving the performance

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THIRD GENERATION (1965-1975)


IC technology improved Improved IC technology helped in designing low cost high speed processor and memory modules Multiprogramming, pipelining concepts were incorporated DOS allowed efficient and coordinate operation of computer system with multiple users Cache and virtual memory concepts were developed

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FOURTH GENERATION (1975-1985)


With VLSI technology a single chip CPU was developed microprocessor Termed as INTEL, MOTOROLA, TEXAS,NATIONAL semiconductors stared developing microprocessor Workstations, microprocessor (PC) & Notebook computers were developed Interconnection LAN,MAN,WAN of different computer for better communication

Computational speed increased by 1000 times


Specialized processors like Digital Signal Processor were also developed

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BEYOND THE FOURTH GENERATION (1985 TILL DATE)


Computers featuring AI High speed processor - Ghz speed

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Chapter 2. Machine Instructions and Programs

Objectives
Machine instructions and program execution, including branching and subroutine call and return operations. Number representation and addition/subtraction in the 2s-complement system. Addressing methods for accessing register and memory operands. Assembly language for representing machine instructions, data, and programs. Program-controlled Input/Output operations.

Number, Arithmetic Operations, and Characters

Signed Integer
3 major representations:
Sign and magnitude Ones complement Twos complement In all three systems, the leftmost bit is 0 for positive and 1 for negative Positive numbers have identical representations in all systems, but negative values have different representations

Signed Integer
Assumptions:
4-bit machine word 16 different values can be represented Roughly half are positive, half are negative

Sign and Magnitude Representation


-7 -6 -5 -4 -3 -2
11 00 10 11 10 10 10 01 11 11 11 10

+0
00 00 +1 00 01 00 10

11 01

+2 +3 +4

+ 0 10 0 = + 4 1 10 0 = - 4 -

00 11 01 00 01 01 01 10 10 00 01 11

+5

-1

+6

-0

+7

High order bit is sign: 0 = positive (or zero), 1 = negative Three low order bits is the magnitude: 0 (000) thru 7 (111) Range = -(2n-1 )-1 to +2n-1 -1 Two representations for 0

Ones Complement Representation


-0 -1 -2 -3 -4 -5
11 00 10 11 10 10 10 01 11 11 11 10

+0
00 00 +1 00 01 00 10

11 01

+2 +3 +4

+ 0 10 0 = + 4 1 01 1 = - 4 -

00 11 01 00 01 01 01 10 10 00 01 11

+5

-6

+6

-7

+7

In 1s complement -ve value is obtained by complementing each bit of the corresponding +ve value The operation of forming 1s complementing is equivalent to subtracting that no. from 2n -1 Still two representations of 0! This causes some problems

Twos Complement Representation


-1 -2
like 1's comp -3 11 01 except shifted one position -4 11 00 clockwise -5 10 11
11 11 11 10

+0
00 00 +1 00 01 00 10

+2 +3 +4

+ 0 10 0 = + 4 1 10 0 = - 4 -

00 11 01 00 01 01 01 10 10 00 01 11

-6

10 10 10 01

+5

-7

+6

-8

+7

The operation of forming 2s complementing is equivalent to subtracting that no. from 2n 2s complement of a no. can be obtained by adding 1 to the 1s complement of that no. Only one representation for 0 One more negative number than positive number

Binary, Signed-Integer Representations


B b 3 b 2 b1 b 0 Sign and magnitude +7 +6 +5 +4 +3 +2 +1 +0 - 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 Values represented 1' s complement +7 +6 +5 +4 +3 +2 +1 +0 -7 -6 -5 -4 -3 -2 - 1 -0 2' s complement + + + + + + + + 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1

1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1

1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1

Figure 2.1. Binary, signed-integer representations.

SUMMARY OF THE TABLE


SIGN & MAGNITUE SYSTEM: Negative value is obtained by changing the sign bit (MSB) Range: -(2n-1 ) -1 to +2n-1 -1 SIGNED 1S COMPLEMENT: Negative number is obtained by complementing each bit of the corresponding positive number i.e (2n-1) N
Range: -(2n-1 ) -1 to +2n-1 -1

SIGNED 2S COMPLEMENT: Negative number is obtained by taking 2s complement of positive number i.e 2n-N Range: - (2n-1) to + (2n-1-1)

Addition of positive numbers


1 +1 -----10 -----1 +0 ------1 --------

ADDITION AND SUBSTRACTION OF SIGNED NUMBERS


For signed arithmetic complement format is used operations 2s

For signed arithmetic operation sign and magnitude and 1s complement format is not suitable

Addition using 2s Complement


0111 + 1101 --------1 0100 -------The carry out should be ignored

Rules for addition and subtraction of n bit signed numbers using 2s complement representation

Addition of two n bit numbers:


Add n bits including sign bit and ignore carry_out from MSB position. Sum will be correct till the answer are within range i.e -2n-1 to +2n-1-1

Subtraction of two n bit numbers:


Eg: X-Y Take 2s complement for Y and add to X X is minuend Y is subtrahend Result will be correct if the answers are within range

If

the results are out of range it is called arithmetic overflow

Example of addition of n bit signed numbers using 2s complement representation +2 +3 + ---+5 ----0010 0011 ---------0101 --------+4 -6 -2 0100 + 1010 ------------1110 --------------6 +3 ----3 ---1010 + 0011 -------1101 ---------

-4 1100 -3 + 1101 --- -------1 1001 -7 --- ----------

Example of subtraction of n - bit signed numbers using 2s complement representation

+4 - +3 -----------+1 -----------+5 - -2 ------+7 --------

0100 0011 --------

0100 + 1101 ------10001 -------- 0101 0010 -------0111 ---------

0101 1110 ---------

Example of subtraction of n bit signed numbers using 2s complement representation

-3 - -6 -----------+3 ------------4 - +2 -------6 --------

1101 1010 --------

1101 0110 ------1 0011 --------1100 + 1110 -------1 1010 ---------

1100 0010 ---------

Example of addition and subtraction of n bit signed numbers using 2s complement representation leading to overflow

+3 - -6 -----------+9 ------------4 + -5 -------9 --------

0011 1010 --------

+ -------

0011 0110 1001 -7 ---------

1100 + 1011 -------1 0111 +7 ---------

ARITHMETIC OVER FLOW


Overflow will not occur when two numbers having opposite signs added

Overflow can occur only if two numbers having same signs are added
The carry out signal from the sign bit position is not a sufficient indicator of overflow when adding signed numbers A simple way to detect the overflow is to examine the signs of the two numbers X and Y and the sign of the result. When both the operands X and Y have the same sign, an over flow occurs when the sign of S is not the same as the signs of X and Y

Memory Locations, Addresses, and Operations

Memory consists of millions of storage cells each capable of storing a bit of information Memory organized in a way such that a group of n bits can be stored or retrieved in a single basic operation n is the word length k-bit address computer generates an address space of 2k locations 24-bit address computer generates an address space of 224
locations i.e 16777216 locations

MEMORY ADDRESSING

Memory Location, Addresses, and Operation


It is impractical to assign distinct addresses to individual bit locations in the memory. The most practical assignment is to have successive addresses refer to successive byte locations in the memory byte-addressable memory. Byte locations have addresses 0, 1, 2, If word length is 32 bits, they successive words are located at addresses 0, 4, 8,

MEMORY ADDRESSING
There are two ways of assigning byte addresses across words

BYTE ADDRESSABILITY

MEMORY ASSIGNMENT

LITTLE ENDIAN

BIG ENDIAN

Big-Endian and Little-Endian Assignments


Big-Endian: lower byte addresses are used for the most significant bytes of the word Eg: INTEL 8085, INTEL 8086 Processor uses this scheme Little-Endian: opposite ordering. lower byte addresses are used for the less significant bytes of the word Eg: Motorola and Power PC Processors
ord W address
0 4 0 4 Byte address 1 5 2 6 3 7 0 4 3 7 Byte address 2 6 1 5 0 4


k k k k k k k k


k k

2 -4

2 -4

2 -3

2- 2

2 - 1

2 - 4

2- 1

2 - 2

2 -3

2 -4

(a) Big-endian assignment

(b) Little-endian assignment

Figure 2.7. Byte and word addressing.

In case of 16 bit data, aligned words begin at byte addresses of 0,2,4,.

In case of 32 bit data, aligned words begin at byte address of 0,4,8,.


In case of 64 bit data, aligned words begin at byte addresses of 0,8,16,.. In some cases words can start at an arbitrary byte address also then, we say that word locations are unaligned

MEMORY OPERATION

LOAD (READ OR FETCH)

STORE (WRITE)

LOAD(READ OR FETCH )
Transfers a copy of the contents of a specific memory location to the processor
Processor sends address of the desired location to memory and requests that its contents be read(Issues read signal) Memory reads the data and sends it to the processor Memory contents remains unchanged

STORE OR WRITE
Transfers an item of info from the cpu to a specific memory location, destroying the former contents of that location

Processor sends the address of the desired location to the memory, together with the data to be written
Issues write signal Sends the data via data bus and write into the selected particular memory location

Instruction and Instruction Sequencing

INSTRUCTIONS AND INSTRUCTION SEQUENCING


A computer must have instructions capable of performing following 4 types of operation Data transfers between the memory and the processor registers Arithmetic and logic operations on data Program sequencing and control I/O transfers

Register transfer notation (RTN)


Memory

locations, registers and I/O register names are identified by a symbolic name in uppercase alphabets
SUM,

LOOK_UP, are memory location which indicates the address of memory location
R1, R2 are register names DATAIN, OUTSTATUS are I/O register names

Contents of a location are denoted by placing square brackets around the name of the location ex:R1[LOC], R3 [R1]+[R2] RHS of RTN always denotes a values, and is called Source LHS of RTN always denotes a symbolic name where value is to be stored and is called destination Source contents are not modified Destination contents are overwritten

Examples of RTN statements

1. R2

[LOCN]

2. R4

[R3] +[R2]

Assembly Language Notation


Another type of notation is required to represent machine instructions and programs. Move LOC, R1 i.e R1*LOC+ Add R1, R2, R3 i.e R3 *R1++*R2+

TYPES OF INSTRUCTION

Assume an addition operation C=A+B

TYPES OF INSTRUCTION

Three address instruction


where A,B,C are memory location

Syntax: Operation source 1, source 2, destination Eg: ADD A,B,C Advantage: Single instruction can perform the complete operation

Disadvantage : Instruction code will be too large to fit in one word location in memory

TWO ADDRESS INSTRUCTION


Syntax : Operation source, destination

Eg:
i.e

Add A,B
B[A]+[B]

Prev instructions can be performed as

MOVE B,C
Add A,C Disadvantage: Single instruction is not sufficient to perform the entire operation. Will not normally fit into one word

ONE ADDRESS INSTRUCTION


Syntax- Operation source/destination

In this type either a source or destination operand is mentioned in the instruction


Other operand is implied to be a processor register called Accumulator Eg: ADD D Prev instrn can be performed as
1. Load A; 2. ADD B; 3. STORE C; ACC ACC memlocation_ C [memlocation _A] (ACC) +(B) (ACC )

If processor supports ALU operations only with registers then the task C=A+B can be performed by the instruction sequence
Move A, Ri

Move
Add Move

B, Rj
Ri, Rj Rj, C

If processor supports ALU operations where one data may be in memory and other in register then the instruction sequence is for ADD A,B,C :
MOVE A, Ri ADD B, Ri MOVE Ri,C

Instruction Execution and StraightLine Sequencing


Address Begin execution here Contents Move A,R0 Add B,R0

i i+4 i+8

3-instruction program segment

Move R0,C

Assumptions: - One memory operand per instruction - 32-bit word length - Memory is byte addressable - Full memory address can be directly specified in a single-word instruction Two-phase procedure -Instruction fetch -Instruction execute

Data for the program

Figure 2.8. A program for C [A] + [B].

PC Program counter: hold the address of the next instruction to be executed

Straight line sequencing: If fetching and executing of instructions is carried out one by one from successive addresses of memory, it is called straight line sequencing.
Major two phase of instruction execution
Instruction fetch phase: Instruction is fetched form memory and is placed in instruction register IR Instruction execute phase: Contents of IR is decoded and processor carries out the operation either by reading data from memory or registers.

Branching

i
i+4 i+8

Move NUM1,R0
Add Add NUM2,R0 NUM3,R0


i + 4n - 4 i + 4n Add NUMn,R0

Move R0,SUM


SUM NUM1 NUM2


NUMn

Figure 2.9. A straight-line program for adding n numbers.

Move

N,R1 R0

Branching
LOOP
Program loop

Clear

Determine address of "Next" number and add "Next" number to R0 Decrement R1

Branch target
Conditional branch

Branch>0 Move

LOOP R0,SUM


SUM N NUM1 n

Figure 2.10. Using a loop to add n numbers.

NUM2


NUM n

Branch instruction are those which changes the normal sequence of execution. Sequence can unconditionally. be changed either conditionally or

Accordingly we have conditional branch instructions and unconditional branch instruction.


conditional branch instruction changes the sequence only when certain conditions are met. Unconditional branch instruction changes the sequence of execution irrespective of condition of the results.

CONDITION CODES
Results of various instructions are stored for subsequent use by conditional instructions

This is done by recording the required info in individual bits, called as condition code flags grouped together in special processor register called as condition code register or status register

CONDITIONAL CODE FLAGS: 1 if results are Negative 0 if results are Positive Z Zero 1 if results are Zero 0 if results are Non zero V Overflow 1 if arithmetic overflow occurs 0 no overflow occurs C Carry 1 if carry and from MSB bit 0 if there is no carry from MSB bit N Negative

Addressing Modes

Generating Memory Addresses


Situations like program looping, branching demand convenient ways of locating memory words or memory operands.
This convenience is being offered by different instructions (of a particular instruction set as defined by the Microprocessor) via various Addressing Modes they support. Suppose a given memory operand address is too large to fit into a given instruction format (i.e., in operand field), then it is the addressing mode (say Register Indirect Mode ) that can resolve this problem.

What is Addressing Mode . . . ?

The different ways in which the location of an operand is specified in an instruction are referred to as addressing modes

Addressing Modes:
Immediate mode Absolute (Direct) mode

Register mode
Indirect mode Indexed mode Relative mode Auto increment mode

Auto decrement mode

Immediate Addressing mode


Here the operand is specified in the instruction itself. An instruction that follows immediate mode has an operand field rather than an address field.

R2

For example: Move 50immediate, R0

R1 50 R0

A common convention say, a pound symbol # has to precede the value of an immediate operand Move #50, R0

Direct Addressing Mode /Absolute Mode


Here operand resides in Memory and its address is given explicitly in the address field of an instruction. This scheme need only one memory reference in addition to instruction fetch cycle and no further calculation is required to compute operand address.

Direct addressing scheme is simple to use and easy to implement without the requirement for additional hardware.

Examples
Move LOC,R0 Load P

Store S

Register Addressing Mode


In this scheme, the operand is the contents of a register appearing in the instruction example Add R1,R2

Register Addressing Mode


Advantages of this scheme :
No memory reference A few bit address to indicate register location

Speedy execution since register is inside the processor


& has low access time. Disadvantages of this scheme : Limited address space as number of registers are less in many of the processors.

The effective address of the operand is the contents of a register or memory location whose address appears in the instruction

Indirect Addressing Mode

By referring to this address (EA), the required operand


can be fetched from memory. Example: Add (A), R0 i.e. EA = (A) i.e. contents of A is B

Here B is effective address of desired operand in memory

Indirect Addressing Mode

Register Indirect Addressing Mode


Here, instruction specifies a register in the CPU whose contents give the effective address of the operand in Memory. For example Add (R1), R0 i.e. EA = (R1) i.e. contents of R1 is B

Address Contents Move Move Clear LOOP Add Add Decrement Branch > 0 Move

N, R1 #NUM, R2 R0 (R2), R0 #4, R2 R1 LOOP R0, SUM

The advantage of Register Indirect Addressing:

It uses one less memory reference (memory read operation) Address field of the instruction uses a fewer bits to specify a register Register indirect addressing can be specified with Effective Address EA = (R) i.e. B Advantages of Indirect addressing: a wider address range to refer to a large number of memory locations. Disadvantage of Indirect addressing: 2 or more memory references (memory read operations) required to fetch the desired operand in memory.

Indexed Addressing Mode


Here, effective address of the operand is generated by adding a constant value to the contents of a register. This constant value may be either an offset value called displacement or beginning address of data/operand array in main memory (Base). Indexed addressing mode is symbolically represented as X(R) Here X denote a constant and R is name of the register involved in Indexing. Effective address EA of the operand is given as EA = X + [R] Contents of index register are not changed during the process of address generation.

Indexed Addressing Mode


Example: Add 20(R1),R2

Add 2000(R3),R4

Assume that a list of scores of the student beginning at location LIST as shown in the following diagram A 4 word memory comprises a record that stores relevant info for each student Compute the sum of all scores obtained on each of the test and store these sums in memory locations SUM1,SUM2,SUM3

Indexed Addressing Mode


N LIST LIST+4 LIST+8 LIST+12 LIST+16 5000 5004 5008 5012 5016 5020 n Student ID Test1 Test2 Test3 Student ID Test1 Test2 Test3 .

LOOP

Move Clear Clear Clear Move Add Add Add Add Decrement Branch>0 Move Move Move

#LIST, R0 R1 R2 R3 N, R4 4(R0), R1 8(R0), R2 12(R0), R3 #16, R0 R4 LOOP R1, SUM1 R2, SUM2 R3, SUM3

Indexed Addressing Mode


Advantages of Index mode

is the flexibility it offers to access relative memory locations


Disadvantages of Index mode * Is the complexity of computing effective address.

* The instruction requires to have two address fields


at least one of which is an explicit number.

Variations of Indexed Addressing Mode


several variations of this basic form provide a very efficient access to memory operands in practical programming situations. For example, a second register may be used to contain the offset X, in which case we can write the Index mode as (Ri, Rj) The effective address is the sum of the contents of registers Ri and Rj. The second register is usually called the base register. This form of indexed addressing provides more flexibility in accessing operands, because both components of the effective address can be changed.

Another version of the Index mode uses two registers plus a constant, which can be denoted as X(Ri, Rj) In this case, the effective address is the sum of the constant X and the contents of registers Ri and Rj. This added flexibility is useful in accessing multiple components inside each item in a record, where the beginning of an item is specified by the (Ri, Rj) part of the addressing mode.

Relative Addressing Mode


This scheme supplies the relative position of the memory operand to be located.

Its like index mode only but program counter register PC


substitutes for base address contents Commonly used to specify the target address in branch

instruction
Relative Mode specify Effective Address by a notation: X(PC) Effective address is EA = [ PC ] + X

Branch > 0 loop Here jump value / displacement X

Auto Increment Mode


The EA of the operand is the contents of a register specified in the instruction After accessing the operand, the contents of this register are incremented automatically to point to the next operand in contiguous memory locations. Notation for Auto Increment Mode: (Ri) + For example: Add (R2) +, R0 Use of Auto Increment mode instruction eliminates the use of explicit increment instruction

Auto Decrement Mode


Here, content of a register specified in the instruction is decremented to denote effective address of next operand in successive memory location. Notation for Auto Decrement Mode: - (Ri) For instance Add (R2), R0 It allows accessing of operands in decreasing order of memory address..

Assembly Language
Here, symbolic codes are used to represent binary pattern of machine instructions. These symbolic codes are called as mnemonics. Mnemonics are abbreviations that represent operation code of an instruction in a compact and meaningful symbolic form. For instance mnemonics for few operation codes include:
INC / INR ADDI ADD LOAD STORE MOVE - Increment - To add immediate operand - To add - To load operand from memory - To store operand to memory - To transfer data from one location to another location/Register.

Assembly Language
A complete set of such mnemonics, symbolic names for register & memory locations and a list of rules for their use forms a programming language called an Assembly Language. The basic unit of assembly language program is a line of code. Here every line of code has symbolic code called mnemonic opcode and symbolic name to represent address of memory location / register as the operand field. The translator program is called an Assembler.

Assembly Language syntax


For example, assembly language syntax suggests that a

move instruction to appear as follows: MOVE R0, SUM The opcode mnemonic MOVE is followed by at least one blank space. The source operand is in register R0 (register operand). The destination operand is in the memory location SUM For instance symbolic name of operand memory location SUM suggest absolute mode or direct addressing mode is used in the instruction.

Assembly Language syntax


Pound sign # usually denotes an immediate operand in the instruction using Immediate Addressing mode For example: ADD #10, R2 or ADDI 10, R2 MOVE #20, R3 Indirect addressing is usually specified by placing parentheses around the name or symbol For example ADD (A), R0

Format of Assembly Language Statements

Assembler Directives
Assembler Directives are the assembler commands to the assembler concerning the program being assembled. These commands are neither translated into machine opcode nor assigned any memory location in the object program. Thus an assembly language program is said to be a complete one and acceptable to an assembler for translation and for further assignment of memory locations if it is associated with necessary assembler directives. Examples of Assembler Directives: S EQU 150 The assembler command EQU directs the assembler during translation that the symbolic name S must be replaced by value 150,

Memory arrangement for the program


100 104 108 112 116 120 124 128 Move N, R1 Move #NUM1,R2 Clear R0 Add (R2), R0 Add #4, R2 Decrement R1 Branch>0 LOOP Move R0, SUM

Memory arrangement for the program


SUM N NUM1 NUM2 200 204 208 212 100

. . . NUMn 604

AL representation for the program


SUM N NUM1 START EQU ORIGIN DATAWORD RESERVE ORIGIN MOVE MOVE CLR R0 ADD ADD DEC BGTZ MOVE RETURN END 200 204 100 400 100 N,R1 #NUM1,R2 (R2),R0 #4,R2 R1 LOOP R0,SUM START

LOOP

Assembler Directives
ORIGIN 204 Instruct assembler to place data block at main memory locations starting from 204 N DATAWORD 100 Inform the assembler that value of N i.e. data value 100 is to be placed in the memory location 204. ORIGIN 100 The second ORIGIN directive states that assembler directive must load machine instructions of the object program in the main memory starting from location 100.

NUM1 RESERVE 400 This directive declares that a memory block of 400 bytes is to be reserved for data, and that the name NUM1 is to be associated with address 208

RETURN This is an assembler directive that identifies the point at which execution of the program should be terminated. It causes the assembler to insert an appropriate machine instruction that returns control to the operating system of the computer.

END START The last statement in the source program is the assembler directive END, which tells the assembler that this is the end of the source program text. The END directive includes the label START, which is the address of the location at which execution of the program is to begin.

ASSEMBLY AND EXECUTION OF PRGRAMS


A source program written in an assembly language must be assembled into a machine language object program before it can be executed performed by assembler As the assembler scans through a source programs, it keeps track of all names and the numerical values that correspond to them in a symbol table

When a name appears a second time, it is replaced with its value from the table A problem arises when a name appears as an operand before it is given a value. For example, this happens if a forward branch is required A simple solution to this problem is to have the assembler scan through the source program twice During the first pass, it creates a complete symbol table. At the end of this pass, all names will have been assigned numerical values The assembler then goes through the source program a second time and substitutes values for all names from the symbol table. Such an assembler is called a two-pass assembler.

The assembler stores the object program on a magnetic disk The object program must be loaded into the memory of the computer before it is executed. This task is performed by an utility program called a loader

NUMBER NOTATION
ADD #93, R1 or ADD #%01011101, R1 or ADD #$5D, R1

Basic Input/Output Operations


Mechanism of I/O transfer between processor and keyboard & video monitor: A character key when pressed from the keyboard its scan code is sent to an 8-bit buffer register DATAIN in the keyboard. Processor is informed about a valid character data presence in DATAIN register by setting a synchronization flag SIN to 1. I/O driver program continuously monitors contents of SIN flag, & when SIN is set to 1, it reads the contents of DATAIN. Thus character stored in DATAIN register is transferred to processor over a system bus and SIN content is automatically reset to 0.

Mechanism of I/O transfer between Processor and Keyboard & Video monitor

A similar set of events take place while transferring a character data from processor to the display screen. Here a DATAOUT register that holds a characters code to be displayed when synchronization control flag SOUT is set to 1. When SOUT equals 1, the display device is ready to receive a character from processor. The transfer of a character to DATAOUT resets SOUT to 0. I/O driver program instructions control the status of SOUT flag.

The buffer registers DATAIN, DATAOUT, and control flags SIN,


in this hardware setup forms parts of a connectivity circuits commonly known as device interface or interface hardware.
SOUT

I/O driver program instructions for I/O data transfer

WRITEWAIT Branch to WRITEWAIT if SOUT = 0 Output from R0 to DATAOUT (if SOUT = 1)

SOUT is set to 1 when display terminal is free to display next character. The wait loop is executed repeatedly until the control flag SOUT is set to 1 by the display terminal. Initial state of SIN is 0 and SOUT is 1

Memory mapped i/o some memory addresses refer to peripheral device buffer registers, such as DATAIN,DATAOUT Data can be transferred b/w the cpu and these registers using same set of instructions and same status flags Ex: MoveByte DATAIN,R0 MoveByte R0,DATAOUT Status flags SIN and SOUT can be included device status register Assume that the bit b3 of the status registers INSTATUS,OUTSTATUS corresponds to SIN and SOUT

Then read and write operation can be implemented as:


READWAIT TestBit #3,INSTATUS Branch=0 READWAIT

MoveByte DATAIN,R0

WRITEWAIT

TestBit

#3,OUTSTATUS

Branch=0 WRITEWAIT

MoveByte R0,DATAOUT

Program to read a line of chars and to display it


Move #LOC,R0

READ

ECHO

TestBit #3,INSTATUS Branch=0 READ MoveByte DATAIN,(R0) TestBit #3,OUTSTATUS Branch=0 ECHO MoveByte (R0),DATAOUT Compare #CR,(R0)+
branch!=0 READ

Stacks Last In First Out List


Stack is used in order to organize the control and info linkage between the program and the subroutine

Stack refers to storage area in which a group of data items


can be stored at consecutive memory locations with the accessing restriction that data elements can be added / stored

or removed / deleted at only one end of the list called top of


stack. This kind of list structure is called Pushdown stack. A special register called Stack Pointer (SP) always points to

the address of top element of the stack.


The two operations that can be performed on a stack are Insertion (PUSH) and Deletion (POP) of data items.

Assume that the stack grows in the decreasing memory


address

SP->

BOTTOM

. . 12 -98 . . 55 . .

2k-1

Stack Operations: PUSH and POP


Suppose, we would like to insert a new element say 356 on to a stack, then PUSH operation to insert 356 can be performed using the instructions: Subtract #4,SP ; SP points to location 104 MOVE NEWITEM, (SP) ; Transfer 356 from location NEWITEM to location 104 Pointed to by SP contents Now let us remove an element from stack. The POP operation to delete an element from top of stack can be performed using the instructions: MOVE (SP), ITEM ; Transfer 356 to location ITEM Add #4,SP ; SP now points to location 108

If the processor has the autoincr and autodecr addressing modes, then push and pop operation can be performed by single operations:

Move NEWITEM,-(SP) Move (SP)+,ITEM

To prevent either the pushing an item on a full stack or popping an item off an empty stack, the single push and pop operation can be replaced by the following instructions: SAFEPOP Compare #2000,SP Branch>0 EMPTYERROR Move (SP)+,ITEM SAFEPUSH Compare #1500,SP Branch<=0 FULLERROR Move NEWITEM,-(SP)

Queue First In First Out List


Data elements are inserted in memory at the increasing order of memory addresses i.e., at the back of Queue. Data elements are retrieved from memory at the decreasing order of memory addresses i.e. from the front end of Queue. Operations such as QINSERT and QDELETE can be performed on a queue to insert and delete & element respectively. Queue could grow continuously in the direction of higher memory addresses Circular buffer can be used to limit the queue to a fixed region in memory A Queue consisting of 6 elements may appear as follows:

Stack Vs. Queue


Stack Queue
Queue is a FIFO list Stack is a LIFO list
One end of the stack is fixed (the bottom), Both ends of a queue move to higher while the other end rises and falls as data are addresses as data are added at the back and pushed and popped. removed from the front

Needs only one pointer register SP Insertions & Deletions are made from only one end i.e., Top of stack Stack operations are PUSH & POP

Needs two pointer registers QF & QE Insertion from back end and Deletion from front end of a Queue Queue operations are QINSERT & QDELETE

Subroutines
A subroutine is a self contained sub-program designed to be used by other larger programs or main programs. A task which is required to be carried out frequently, is usually implemented as a subroutine. Subroutine mechanisms make use of two kinds of branch instructions: First, a call instruction that branches from the present location in calling program or main program to the location in main memory at which subroutine begins. Second, a return instruction that returns from the subroutine to the location in calling program or main program from which it was called.

The common places for storing the return addresses: Link register

Call-is a special branch instruction which performs the following sequence of operations: 1. Copy the contents of PC (i.e. address of next instruction in sequence following a call instruction in a main program) to link register 2. Transfer control to the beginning of subroutine (the starting address of subroutine is specified in the Call instruction itself)

Return is a special branch instruction which performs : Transfer control to the return address contained in link register.

The way in which a computer makes it possible to call and return from subroutines is referred to as its subroutine linkage method.

Subroutines Nesting & Processor Stack


In case of nesting of subroutines a main program calls a subroutine, and called subroutine can make a call to another subroutine inturn. This continues likewise, to extend nesting of subroutine to any number of levels. Here successive return addresses must be stored safely to allow processor to resume program execution at different places from which subroutine calls have been made. Return addresses hence generated are to be stored and used in a Last-in First out order. This kind of return address behavior associated with subroutine call and return suggest that all such return addresses must be pushed down to a stack called a processor stack rather than using a Link register.

These return addresses are popped up inturn in a manner that suites subroutines return address behaviour for resuming calling program execution. For example : Execution of main program (MAIN) take place in the following sequence of program segments:

Nested Subroutine Call & Return

Parameter Passing
When a program calls a subroutine, it must supply the necessary operands or data to be operated upon by the instructions of called subroutine. These operands are referred to as parameters or arguments. There are many ways of parameter passing such as pass by value, pass by reference etc. Parameters can be placed in register, memory location or processor stack from where they can be accessed by subroutine

Passing parameters through registers


Straight forward and efficient Only few parameters can be passed as the no. registers are limited

Example
Move N,R1 Move #NUM1,R2 Call LISTADD Move R0,SUM LISTADD LOOP Clear R0 Add (R2)+,R0 Decrement R1 Branch>0 LOOP Return

Passing parameters using stack


If many parameters are involved, there not may be enough registers available for passing them to subroutine A stack can be used in such situations

Example
Move #NUM1,-(SP) Move N,-(SP) Call LISTADD Move 4(SP),SUM Add #8,SP

LISTADD

LOOP

MoveMultiple R0-R2,-(SP) Move 16(SP),R1 Move 20(SP),R2 Clear R0 Add (R2)+,R0 Decrement R1 Branch>0 LOOP Move R0,20(SP) MoveMultiple (SP)+,R0-R2 Return

Top of stack level 3

[R2] [R1] [R0]

level 2

Return Address N

NUM1
level 1

Stack Frame
The consecutive location on stack that hold list of parameter including local variables and return address pertaining to a subroutine call & return, constitute a private work space called stack frame of the subroutine. The stack frame locations get filled as and when each subroutine is called for execution. Also, stack frame space is vacated soon after the completion of execution of subroutine it is useful to have another pointer register, called the frame pointer (FP), for convenient access to the parameters passed to the subroutine and to the local memory variables used by the subroutine The pointers SP and FP are manipulated as the stack frame is built, used, and dismantled for a particular of the subroutine.

Assume that SP point to the old top-of-stack (TOS) element Assume that four parameters are passed to the subroutine, three local variables are used within the subroutine, and registers R0 and R1 need to be saved because they will also be used within the subroutine. Before the subroutine is called, the calling program pushes the four parameters onto the stack The call instruction is then executed, resulting in the return address being pushed onto the stack.

Now, SP points to this return address, and the first instruction of the subroutine is about to be executed. This is the point at which the frame pointer FP is set to contain the proper memory address. Since FP is usually a general-purpose register, it may contain information of use to the Calling program. Therefore, its contents are saved by pushing them onto the stack Since the SP now points to this position, its contents are copied into FP

Thus, the first two instructions executed in the subroutine are Move FP, -(SP) Move SP, FP After these instructions are executed, both SP and FP point to the saved FP contents Space for the three local variables is now allocated on the stack by executing the instruction Subtract #12, SP Finally, the contents of processor registers R0 and R1 are saved by pushing them onto the stack. At this point, the stack frame has been set up as shown in the fig.

SP

FP

Saved [R1] Saved [R0] Localvar3 Localvar2 Localvar1 Saved [FP] Return address Param1 Param2 Param3 Param4

Old TOS

The subroutine now executes its task. When the task is completed, the subroutine pops the saved values of R1 and R0 back into those registers, removes the local variables from the stack frame by executing the instruction. Add #12, SP And pops the saved old value of FP back into FP. At this point, SP points to the return address, so the Return instruction can be executed, transferring control back to the calling program.

Calling program is responsible for removing the parameters from the stack frame, some which may be the results passed back by the subroutine The SP now points to the old TOS

Stack frames for nested subroutines


An example of a main program calling a first subroutine SUB1, which then calls a second subroutine SUB2. The stack frames corresponding to these two nested subroutines are shown in the following diagram All parameters involved in this example are passed on the stack.

The flow of execution is as follows. The main program pushes the two parameters param2 and param1 onto the stack in that order and then calls SUB1. This first subroutine is responsible for computing a single answer and passing it back to the main program on the stack. During the course of its computations, SUB1 calls the second subroutine, SUB2, in order to perform some subtask. SUB1 passes a single parameter param3 to SUB2 and gets a result passed back to it.

After SUB2 executes its Return instruction, this result is stored in register R2 by SUB1. SUB1 then continues its computations and eventually passes the required answer back to the main program on the stack. When SUB1 executes its return to the main program, the main program stores this answer in memory location RESULT and continues with its computations at next instruction.

flow of execution The first actions performed by each subroutine are to set the frame pointer, after saving its previous contents on the stack, and to save any other registers required. SUB1 uses four registers, R0 to R3, and SUB2 uses two registers, R0 and R1. These registers and the frame pointer are restored just before the returns are executed.

The Index addressing mode involving the frame pointer register FP is used to load parameters from the stack and place answers back on the stack. The byte offsets used in these operations are always 8, 12, . . . , as discussed for the general stack frame Finally, note that the calling routines are responsible for removing parameters from the stack. This is done by the Add instruction in the main program, and by the Move instruction at location 2164 in SUB1.

LOGIC INSTRUCTIONS
Logic operations are applied to individual bits, are the basic building blocks of digital circuits
AND OR NOT

Not dst

SHIFT AND ROTATE INSTRUCTIONS


There are many applications that require the bits of an operand to be shifted right or left some specified number of bit positions. The details of how the shifts are performed depend on whether the operand is a signed number or some more general binary-coded information. For general operands, a logical shift is used For a number, an arithmetic shift is used, which preserves the sign of the number.

Logical shifts

Two logical shift instructions shifting left (LShiftL) shifting right (LShiftR) These instructions shift an operand over a number of bit positions specified in a count operand contained in the instruction. The general form of a logical left shift instruction is LShiftL count, dst

Logical shift left LShiftL #2, R0


C R0

Before:
0 0 1 1 1 0 . . . 0 1 1

After:

1 1 0 . . . 0 1 1 00

Logical shift right LShiftR #2, R0 0


Before:

R0

0 1 1 1 0 . . . 0 1 1

After:

0 0 0 1 1 1 0 . . . 0

Digit-Packing Example
Suppose that two decimal digits represented in ASCII code are located in memory at byte locations LOC and LOC + 1. Each of these digits should be represented in the 4-bit BCD code and store both of them in a single byte location PACKED. This result is said to be in packed-BCD format. The rightmost four bits of the ASCII code for a decimal digit correspond to the BCD code for the digit.

Hence, the required task is to extract the loworder four bits in LOC and LOC + 1 and concatenate them into the single byte at PACKED. The instruction sequence accomplishes the task using register R0 as a pointer to the ASCII characters in memory, and using registers R1 and R2 to develop the BCD digit codes.

When a MoveByte instruction transfers a byte between memory and a 32-bit processor register, the byte is located in the rightmost eight bit positions of the register. The And instruction is used to mask out all but the four rightmost bits in R2.

Arithmetic shifts
Arithmetic shift right AShiftR #2, R0
R0

Before:
1 0 0 1 1 . . . 0 10 0

After:

1 1 1 0 0 1 1 . . . 0

Rotate Operations
In the shift operations, the bits shifted out of the operand are lost, except for the last bit shifted out which is retained in the Carry flag C. To preserve all bits, a set of rotate instructions can be used. They move the bits that are shifted out of one end of the operand back into the other end Two versions of both the left and right rotate instructions are usually provided. In one version, the bits of the operand are simply rotated. In the other version, the rotation includes the C flag.

Rotate left without carry RotateL #2, R0


C R0

Before:
0 0 1 1 1 0 . . . 0 1 1

After:

1 1 0 . . . 0 1 1 0 1

Rotate left with carry RotateLC #2, R0


C R0

Before:
0 0 1 1 1 0 . . . 0 1 1

After:

1 1 0 . . . 0 1 1 00

Rotate right without carry RotateR #2, R0

R0 C

Before:
0 1 1 1 0 . . . 0 1 1 0

After:

1 1 0 1 1 1 0 . . . 0

Rotate right with carry RotateRC #2, R0

R0 C

Before:
0 1 1 1 0 . . . 0 1 1 0

After:

1 0 0 1 1 1 0 . . . 0

Multiplication & Division


Some of the processors instruction sets supports Multiply and Divide operations. For which they offer direct instructions to multiply and/or divide on processor register operands. For instance

MULTIPLY Ri, Rj
DIVIDE Ri, Rj

;Rj [Ri] * [Rj]


;Rj [Rj] / [Ri]

Encoding of Machine Instructions


An instruction in Machine language is encoded as sequence of binary digits pattern in a precise and compact form. Machine instructions can be encoded as 8-bit byte, 16-bit half word or 32-bit word. This encoding of machine instruction also depends on wordlength of the machine and has considerable influence on instructions types

8
Opcode

7
Source

7
Dest

10
Other info

one-word instruction
Opcode Source Dest Other info

Memory address/Immediate operand

two-word instruction three-operand instruction


Op code info Ri Rj Rk Other

Two approaches: CISC & RISC CISC: A computer or a processor with a large number of instructions and incorporating variable length instruction formats (i.e. using multiple words for instructions) is termed a Complex Instruction Set Computer abbreviated as CISC

Encoding of Machine Instructions


Salient feature of CISC architecture include: Support large number of instructions 100 to 250 Support wide variety of addressing modes 5 to 20 Comprises variable length instructions Provide instructions for direct manipulation of operands residing in memory Provide single complex instructions that resemble and /or transform a complete statement execution in a high level language programs. Examples of CISC architecture computers: DEC VAX computer, IBM 370 computer Examples of CISC processors Motorola 68000, 68020, 68030, 68040 processors Intel 80 x 86, 80386, 80486, Pentium processors

Salient feature of RISC architecture : A computer or processor with relatively small set of instruction and incorporating fixed length instruction format most of them being a register to register operations, is termed as Reduced Instructions Set Computer abbreviated as RISC Features of RISC architecture include: Support relatively few instructions and are less complex Support few addressing modes Comprises fixed length instructions that can be easily decoded A restriction to perform all operations in processor registers only.

RISC Architecture features:


Memory is accessed with only Load and Store

instructions
Ability to execute one instruction per clock cycle Examples of RISC processors

Power PC 601, 603, 604, 620


Alpha (AXP) processors, DEC 21064 processor

End of unit 2

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