CMOS VLSI Design

Lecture # 1
VLSI Design
Prepared by
S.Sathishkumar
A.M.Sudha
Lecturer/EEE

CMOS VLSI Design
VLSI:Very Large Scale Integration
Integration: Integrated Circuits
multiple devices on one substrate
How large is Very Large?
SSI (small scale integration)
7400 series, 10-100 transistors
MSI (medium scale)
74000 series 100-1000
LSI 1,000-10,000 transistors
VLSI > 10,000 transistors
ULSI/SLSI (some disagreement)

CMOS VLSI Design
Integration Improves the Design
Lower parasitics, higher clocking speed
Lower power
Physically small

Integration Reduces Manufacturing Costs
(almost) no manual assembly
About $1-5billion/fab
Typical Fab ~1 city block, a few hundred people
Packaging is largest cost
Testing is second largest cost
For low volume ICs, Design Cost may swamp
all manufacturing cost
WHY VLSI?
CMOS VLSI Design
What is a Silicon Chip?
A pattern of interconnected switches and gates on the surface of a
crystal of semiconductor (typically Si)
These switches and gates are made of
areas of n-type silicon
areas of p-type silicon
areas of insulator
lines of conductor (interconnects) joining areas together
Aluminium, Copper, Titanium, Molybdenum, polysilicon, tungsten
The geometryof these areas is known as the layout of the chip
Connections from the chip to the outside world are made around the
edge of the chip to facilitate connections to other devices
CMOS VLSI Design
Y - Chart
CMOS VLSI Design

Specifications
IO, Goals and Objectives, Function, Costs

Architectural Description
VHDL, Verilog, Behavioral, Large Blocks

Logic Design
Gates plus Registers

Circuit Design
Transistors sized for power and speed
Discrete Logic, Technology Mapping

Layout
Size, Interconnect, Parasitics
Levels of Design
CMOS VLSI Design
n+ n+
S
G
D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
CMOS VLSI Design
Physical Design Cycle
The process of converting specifications of an electrical circuit into
a layout
Physical Design Cycle
Circuit Design
Fabrication
Floorplanning & Placement
Pin Assignment
Compaction
Partitioning
Routing
n+ n+
S
G
D
CMOS VLSI Design
Partitioning
Decomposition of a system into a set of smaller subsystems
without affecting its original functionality
Factors
Memory space requirements
Computation Power
Parameters
Interconnections between partitions
Delay due to partitioning
Number of terminals
Area of each partition
Number of partitions
CMOS VLSI Design
Floorplanning & Placement
Assigning locations to the blocks on a layout surface
Floorplanning All/Some blocks are flexible
Placement All bocks are fixed
Factors
Layout area
Completion of routing
Circuit performance
Parameters
Shape of the blocks
Routing considerations
Placement for high performance circuits
Packaging considerations
Pre-placed blocks
CMOS VLSI Design
Routing
Finding the geometric layout of all the nets
Global & Detailed Routing
Factors
Regions channel & switchbox
Nets signal nets, clock nets, power & ground nets
Parameters
Number of terminals
Net width
Via restrictions
Boundary type
Number of layers
Net types
CMOS VLSI Design
Compaction
Minimizing the total layout area without violating any design rules
Removing the vacant space without altering the functionality of
the layout.
Factors
Fabrication process
Design rules
Methods
Reducing spacing between the features
Reducing the size of each feature
By reshaping the features
CMOS VLSI Design
Design Styles
Full custom
Standard cell
Gate-array
Macro-cell
FPGA
Combinations
CMOS VLSI Design
Full Custom
Hand drawn geometry
All layers customized
Digital and analog
Simulation at transistor level (analog)
High density
High performance
Long design time
CMOS VLSI Design
Full Custom
IN Out
Vdd
Gnd
CMOS VLSI Design
Standard cells
Standard cells organized in rows (and, or, flip-flops,etc.)
Cells made as full custom by vendor (not user).
All layers customized
Digital with possibility of special analog cells.
Simulation at gate level (digital)
Medium density
Medium-high performance
Reasonable design time
CMOS VLSI Design
High performance devices
Mixture of full custom, standard cells and macros
Full custom for special blocks: Adder (data path), etc.
Macros for standard blocks: RAM, ROM, etc.
Standard cells for non critical digital blocks
CMOS VLSI Design
Dual port RAM
Full custom
Standard cell
ASIC with mixture of full custom,RAM and standard cells
FIFO
Single port RAM
CMOS VLSI Design
Pentium
CMOS VLSI Design
ALPHA & MOTOROLA POWER PC
Alpha
CMOS VLSI Design
New combinations
FPGAs with RAM, PCI interface, Processor, ADC, etc.
Gate arrays with RAM, Processor, ADC, etc
Processor
RAM
FPGA or Gate-array logic
CMOS VLSI Design
MOS Transistor
n+ n+
p-substrate
Field-Oxyde
(SiO
2
)
p+ stopper
Polysilicon
Gate Oxyde
Drain
Source
Gate
Bulk Contact
CROSS-SECTION of NMOS Transistor
CMOS VLSI Design
nMOS Transistor
Four terminals: gate, source, drain, body
Gate oxide body stack looks like a capacitor
Gate and body are conductors
SiO
2
(oxide) is a very good insulator
Called metal oxide semiconductor (MOS) capacitor
Even though gate is
no longer made of metal
n+
p
Gate Source Drain
bulk Si
SiO
2
Polysilicon
n+
CMOS VLSI Design
nMOS Operation
Body is commonly tied to ground (0 V)
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
n+
p
Gate Source Drain
bulk Si
SiO
2
Polysilicon
n+
D
0
S
CMOS VLSI Design
nMOS Operation Cont.
When the gate is at a high voltage:
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from source through
channel to drain, transistor is ON
n+
p
Gate Source Drain
bulk Si
SiO
2
Polysilicon
n+
D
1
S
CMOS VLSI Design
pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (V
DD
)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
SiO
2
n
Gate Source Drain
bulk Si
Polysilicon
p+ p+
CMOS VLSI Design
MOS Transistor Symbols
D
S
G
D
S
G
G
S
D D
S
G
NMOS - Enhancement
NMOS - Depletion
B
NMOS with Bulk
Contact
PMOS - Enhancement
CMOS VLSI Design
MOS DC Equations
n
+
n
+
p-substrate
D
S
G
B
V
GS
x
L
V(x)
+
V
DS
I
D
MOS transistor and its bias conditions
CMOS VLSI Design
Ideal Transistor I-V
Shockley 1
st
order transistor models
( )
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V
|
|

<

| |
= <
|
\ .

>

CMOS VLSI Design

Channel Length Modulation
Reverse-biased p-n junctions form a
depletion region
Region between n and p with no carriers
Width of depletion L
d
region grows with
reverse bias
L
eff
= L L
d
Shorter L
eff
gives more current
I
ds
increases with V
ds
Even in saturation
n+
p
Gate Source Drain
bulk Si
n+
V
DD
GND
V
DD
GND
L
L
eff
Depletion Region
Width: L
d
CMOS VLSI Design
Pass Transistor

Primary inputs drive both gate and source/drain terminals
NMOS switch closes when the gate input is high









Remember - NMOS transistors pass a strong 0 but a weak 1
A B
X Y
X = Y if A and B
X Y
A
B
X = Y if A or B
CMOS VLSI Design
nMOS Inverter
CMOS VLSI Design
Vdd
Vss
Vo
Vin
R
Pull-Up
Pull Down
Basic Inverter: Transistor with source
connected to ground and a load resistor
connected from the drain to the positive
Supply rail
Output is taken from the drain and control
input connected between gate and ground
Resistors are not easily formed in silicon
- they occupy too much area

Transistors can be used as the pull-up device
CMOS VLSI Design
Vdd
Vss
Vo
Vin
D
S
D
S
Pull-Up is always on Vgs = 0; depletion
Pull-Down turns on when Vin > Vt
NMOS Depletion Mode Transistor Pull - Up
Vt
V0
Vdd
Vi
With no current drawn from outputs, Ids
for both transistors is equal
Non-zero output
CMOS VLSI Design
V
gs
=0.2V
DD

V
gs
=0.4 V
DD

V
gs
=0.6 V
DD

V
gs
=0.8V
DD

V
gs
=V
DD

I
ds

V
ds

V
DD

V
o

V
DD

V
DD

V
in

I
ds

V
DD
V
ds


I
ds

V
ds

V
gs
=-0.6V
DD

V
gs
=-0.4 V
DD

V
gs
=-0.2 V
DD

V
gs
=0
V
gs
=0.2V
DD

CMOS VLSI Design
V
o

V
DD

V
DD

V
in

Vinv
Point where Vo = Vin is called Vinv
Decreasing
Zpu/Zpd
Increasing
Zpu/Zpd
Transfer Characteristics and Vinv can be shifted by altering ratio
of pull-up to Pull down impedances
CMOS VLSI Design
When cascading logic devices care must be taken
to preserve integrity of logic levels

i.e. design circuit so that Vin = Vout = Vinv
Pull-Up to Pull-Down Ratio for an nMOS
Inverter
Determine pull up to pull-down ratio for driven inverter
CMOS VLSI Design
Assume equal margins around inverter; Vinv = 0.5 Vdd
Assume both transistors in saturation, therefore: I
ds
= K (W/L) (V
gs
V
t
)
2
/2
Depletion mode transistor has gate connected to source, i.e. V
gs
= 0

I
ds
= K (W
pu
/L
pu
) (-V
td
)
2
/2

I
ds
= K (W
pd
/L
pd
) (V
inv
V
t
)
2
/2
Enhancement mode device Vgs = Vinv, therefore
Assume currents are equal through both channels (no current drawn by load)

(W
pd
/L
pd
) (V
inv
V
t
)
2
= (W
pu
/L
pu
) (-V
td
)
2


Convention Z = L/W

V
inv
= V
t
V
td
/ (Z
pu
/Z
pd
)
1/2


Substitute in typical values V
t
= 0.2 V
dd
; V
td
= -0.6 V
dd
; Vinv = 0.5 V
dd
This gives Zpu / Zpd = 4:1 for an nmos inverter directly driven by another inverter
CMOS VLSI Design
Vdd Vdd
A B
C
Inverter 1 Inverter 2
Vin1
Vout2
Pull-Up to Pull-Down Ratio for an nMOS inverter
driven through 1 or more pass transistors
It is often the case that two inverters are connected via a series of switches (Pass Transistors)
We are concerned that connection of transistors in series will degrade the logic levels into
Inverter 2. The driven inverter can be designed to deal with this. (Zpu/Zpd >= 8/1)


CMOS VLSI Design
What is CMOS VLSI?
MOS = Metal Oxide Semiconductor (This used to mean a
Metal gate over Oxide insulation)

Now we use polycrystalline silicon which is deposited on
the surface of the chip as a gate. We call this poly or
just red stuff to distinguish it from the body of the chip,
the substrate, which is a single crystal of silicon.

We do use metal (aluminum) for interconnection wires on
the surface of the chip.
CMOS VLSI Design
CMOS:Complementary MOS
Means we are using both N-channel and P-channel type
enhancement mode Field Effect Transistors (FETs).
Field Effect- NO current from the controlling electrode
into the output
FET is a voltage controlled current device
BJT is a current controlled current device
N/P Channel - doping of the substrate for increased
carriers (electrons or holes)

CMOS VLSI Design
CMOS Inverter
A Y
0
1
V
DD
A Y
GND
A Y
CMOS VLSI Design
CMOS Inverter
A Y
0
1 0
V
DD
A=1 Y=0
GND
ON
OFF
A Y
CMOS VLSI Design
CMOS Inverter
A Y
0 1
1 0
V
DD
A=0 Y=1
GND
OFF
ON
A Y
CMOS VLSI Design
CMOS Inverter Properties
High Noise Margins
V
OH
and V
OL
are V
DD
and GND respectively.
Comparable Rise and Fall Times
Under the appropriate scaling conditions
Propagation delay function of load capacitance and resistance of
transistors
No static power dissipation
There never exists a direct path between V
DD
and V
SS
(GND) in
steady state mode.
Symmetrical VTC
Direct path current during switching
Full rail-to-rail swing
CMOS VLSI Design
CMOS Inverter (Switch Model)
R
on
|V
GS
| < |V
T
|
|V
GS
| > |V
T
|
|V
GS
|
CMOS VLSI Design
CMOS Inverter
(Steady State Response)
V
DD
V
DD
V
out
V
out
V
in
= V
DD
V
in
= 0
R
on
R
on
V
OH
= V
DD
V
OL
= 0
V
M
=
R
onp
) f(R
onn
,
CMOS VLSI Design
I-V Characteristics
Make pMOS is wider than nMOS such that |
n
= |
p
V
gsn5
V
gsn4
V
gsn3
V
gsn2
V
gsn1
V
gsp5
V
gsp4
V
gsp3
V
gsp2
V
gsp1
V
DD
-V
DD
V
dsn
-V
dsp
-I
dsp
I
dsn
0
CMOS VLSI Design
CMOS Inverter
(Load Characteristics)
I
n,p
V
in
= 5
V
in
= 4
V
in
= 3
V
in
= 0
V
in
= 1
V
in
= 2
NMOS
PMOS
V
in
= 0
V
i n
= 1
V
in
= 2
V
in
= 3
V
in
= 4
V
in
= 4
V
in
= 5
V
in
= 2
V
in
= 3
CMOS VLSI Design
V(x)
V(y)
V
OH
V
OL
V
M

V
OH
V
OL
f
V(y)=V(x)
Switching Threshold
Nominal Voltage Levels
V(y) V(x)
CMOS Inverter (VTC Characteristics)
CMOS VLSI Design
CMOS Inverter (Operating regions)
Transistor operating regions
Region nMOS pMOS
A Cutoff Linear
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff
C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp
CMOS VLSI Design
Beta Ratio
If |
p
/ |
n
= 1, switching point will move from V
DD
/2
Called skewed gate
Other gates: collapse into equivalent inverter
V
out
0
V
in
V
DD
V
DD
0.5
1
2
10
p
n
|
|
=
0.1
p
n
|
|
=
CMOS VLSI Design
CMOS Inverter (VTC Characteristics)
"1"
"0"
V
OH
V
IH
V
IL
V
OL
Undefined
Region
V(x)
V(y)
V
OH
V
OL
V
IH
V
IL
Slope = -1
Slope = -1
CMOS VLSI Design
Noise Margins
How much noise can a gate input see before it does not
recognize the input?
Indeterminate
Region
NM
L
NM
H
Input Characteristics Output Characteristics
V
OH
V
DD
V
OL
GND
V
IH
V
IL
Logical High
Input Range
Logical Low
Input Range
Logical High
Output Range
Logical Low
Output Range
CMOS VLSI Design
CMOS Inverter (Noise Margin)
V
IH
V
IL
Undefined
Region
"1"
"0"
V
OH
V
OL
NM
H
NM
L
Gate Output
Gate Input
Noise Margin High
Noise Margin Low
CMOS VLSI Design
MOS Transistor Model
D
S
G
B
C
GD
C
GS
C
SB
C
DB
C
GB
CMOS VLSI Design
Gate Capacitance
S
D
G
C
GC
S
D
G
C
GC
S
D
G
C
GC
Cut-off
Resistive Saturation
Most important regions in digital design: saturation and cut-off
CMOS VLSI Design


Thank you