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Lecture 6, 7
*
P Q R ORG DC.W DC.W DS.W END $500 2 4 1 $400
ORG MOVE ADD MOVE STOP ORG P: Q: R: $500 DC.W DC.W DS.W END
Mnemonic or assembler Directive field
2 4 1 $400
Operand field
$1001 $1002
14
Width Perim
Data area
MOVE.B Size,D0 ADD.B Width,D0 ADD.B D0,D0 MOVE.B D0,Perim STOP #$2700 Program area
Example of drawing a memory map: relationship between a source program, assembled program, and memory map
1 2 3 4 5 6 7 8 9 10 11
00001000 00001000 00001001 00001002 00001200 00001200 00001204 00001208 0000120A 0000120E
ORG DC.B DC.B DS.B ORG MOVE.B ADD.B ADD.B MOVE.B STOP END
Example of drawing a memory map: relationship between a source program, assembled program, and memory map
This program uses two define-constant directives to set up constants called Size and Width in memory These two constants are 25 and 14, which are represented in hexadecimal as $19 and $0E, respectively These two define-constants are 1-byte directives each and hence are loaded at addresses $1000 and $1001, respectively The define-storage assembler directive, Perim DS.B 1, reserves a one-byte location called Perim at $1002
Example of drawing a memory map: relationship between a source program, assembled program, and memory map
The second ORG directive resets the assemblers location counter to $1200 The first instruction, MOVE.B Size,D0, copies the contents of memory location Size to data register D0 The next instruction adds the contents of memory location Width to the contents of D0 The result is then doubled The operation MOVE.B D0,Perim copies the result into the memory location Perim
1007
1008 1009 100A 100B
100E
1010 1012 1014 1016
101C
1020 1024 1028 102C
PC
X N Z V C CCR
Data registers
The 68K has eight general-purpose data registers, numbered D0 to D7 Any operation that can be applied to data register Di can also be applied Dj There are no special purpose data registers reserved for certain types of instruction When a byte operation is applied to the contents of a data register, only bits D00 to D07 of the register are affected, similarly, a word operation affects bits D00 to D15. Only the lower-order byte (word) of a register is affected by a byte (word) operation
Data registers
For example, applying a byte operation to data register D1 affects only bits 0 to 7 and leaves bits 8 to 31 unchanged. CLR.B D1 forces the contents of D1 to XXXX XXXX XXXX XXXX XXXX XXXX 0000 0000
Address registers
The 68K has eight 32-bit address registers, called A0 to A7, which act as pointer registers Registers A0-A6 are identical in that whatever we can do to Ai, we can also do to Aj. Address register A7 has an additional function of being used as a stack pointer for the storage of subroutine addresses Operations on address registers do not affect the 68Ks condition code register
Address registers
The contents of an address register is considered to be a single entry, byte and word divisions of address registers are meaningless All operations on an address register are longword operations .W operations are automatically extended to .L Addresses are treated as signed twos complement values. If we perform operation on the lower-order word of an address register, the sign bit is extended from A15 to bits A16 to A31.
Address registers
For instance the operation
MOVEA.W #$8022,A3
Address registers
Positive and negative addresses can seem strange but in fact positive address can be thought of meaning forward and negative address meaning backward E.g., A1 contains the value 1280 and A2 contains the value 40 (stored as the appropriate twos complement value). Adding the contents of A1 to the contents of A2 by ADDA.L A1,A2 to create a composite address results in the value 1240, which is 40 locations back from the address pointed at by A1
MOVE P,Di
[Di]<-[M(P)]
MOVE Di,N
[M(N)]<-[Di]
EXG Di,Dj
[Temp]<-[Di],[Di]<-[Dj],[Dj]<-[Temp]
SWAP Di
[Di(0:15)]<-[Di(16:31)],[Di(16:31)]<-[Di(0:15)]
LEA P,Ai
[Ai]<-P
Operand
(a 0 enters the least-significant bit and the mostsignificant bit is copied to the C and X flags in the CCR
Logical shift right (a 0 enters the most-significant bit and the leastsignificant bit is copied to the C and X flags in the CCR
LSR 0 Operand C X
Operand
(a 0 enters the least-significant bit and the mostsignificant bit is copied to the C and X flags in the CCR
Arithmetic shift right (the old mostsignificant bit is copied into the new most-significant bit and the leastsignificant bit is copied to the C and X flags in the CCR
Operand
Rotate left the most-significant bit is copied into the leastsignificant bit and the carry flag Rotate right the least-significant bit is copied into the mostsignificant bit and the carry flag
ROR Operand C
Operand
Rotate left through extend the most-significant bit is copied into the X and C flags in the CCR and the old X bit into the leastsignificant bit
ROXR
X Operand C
Rotate right through extend the least-significant bit is copied into the X and C flags in the CCR and the old X bit into the mostsignificant bit
The EOR operation is used to toggle one or more its of a word. EORing a bit with 0 has no effect, and EORing it with 1 inverts it.
if [D0]=1100 1010, the operation EOR.B #%1111 0000, D0 results in [D0]=0011 1010
ERROR EXIT The unconditional branch instruction BRA EXIT forces the computer to execute the next instruction at EXIT and skips past the ERROR clause.
4
5 6 7 8 9 A B C D E F
34
35 36 37 38 39 41 42 43 44 45 46
0100
0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
NotEqu exit
Action2
Action1
Action2 EXIT
Action1
Perform Action1
EXIT
#N,I
EXCEPTION I,D0 #4,D0 Table,A0 (A0,D0),A0 (A0),A0 (A0) <address> <address0> <address1> <address2>
Test for I out of range IF I>N THEN exception Pick up value of I in D0 Each address is a longword A0 points to table of addresses A0 now points to case 1 in table A0 contains address of case 1 handler Execute case 1 handler Here is Address Address Address the table of case 0 of case 1 of case 2 of exceptions handler handler handler
NDC.L
...
<addressN>
Addressing modes
Addressing modes are concerned with how an operand is located by the CPU. A computers addressing modes are almost entirely analogous to human addressing modes, as the following example demonstrate:
Heres 100 USD (literal value) Get the cash from 12 North Street (absolute address) Go to 10 East Street and they will tell you where to get the cash (indirect address) Go to 2 North Street and get the cash from the fifth house to the right (relative address)
Addressing modes
These four addressing modes show that we can provide data itself (i.e. the $100 cash), say exactly where it is, or explain how you go about finding where it is Up to now we have dealt largely with the absolute addressing mode, in which the actual address in memory of an operand is specified by the instruction, or with register direct addressing in which the address of an operand is a register
Addressing modes
We now introduce other ways of specifying the location of an operand. Because the address of an operand can be calculated in several ways, we use the term effective address as a general expression for the address of an operand
Remember that [1234] is a shorthand for [M(1234)] and means the contents of memory location 1234
y x
1000 1001
x y
Data Data
The higher level language FOR... construct can readily by translated into 68K assembly language.
EQU 10 ... MOVE #1,D0 NEXT ... ... ... ... ADD #1,D0 #N+1,D0 BNE NEXT
Define the loop size weve used N=10 here Load D0 with initial value of the loop counter
Body of loop
Increment the loop counter CMP Test for the end of the loop IF not end THEN repeat loop
At the end of the loop, the counter is incremented by means of the instruction ADD #1,D0. The counter D0 is then compared with its terminal value by CMP #N+1,D0 On the last time round the loop, the variable I becomes N+1 after incrementing and the branch to NEXT is not taken, allowing the loop to be exited