Comb Cir

Combinational Circuits
Arithmetic / logic circuit Comparators / parity generators Multiplexers / demultiplexers Encoders / decoders
10/28/2013
Digital Logic Version 1.0
Arithmetic circuit- Half adder

A, B as input, Sum and Cy as output The truth table is as below
A
0 0
B
0 1
SUM
0 1
CY
0 0
1
1
0
1
1
0 1 0
0
1 0 1
1 = AB` 0 SUM + A`B 1 0
Cy 1= AB
1
10/28/2013
1
1
0
1
1
1
2
Half Adder Circuit

Sum =A B = Sum , Carry=AB
A B Sum EXOR
Carry
AND
10/28/2013 Digital Logic Version 1.0 3
Full Adder
Full Adder with input A, B and C. Outputs are Sum and Carry.
A
0
B
0
C
0
SUM
0
CY
0
0
0 0 1
0
1 1 0
1
0 1 0
1
1 0 1
0
0 1 0
1
1 1
10/28/2013
0
1 1
1
0 1
0
0 1
1
1 1
4
Karnaugh Map ...

AB C C` 0 A`B`
00
0
A`B 01
0
AB
AB`
11 1
10
0
C 1
Cy = AB + BC + AC
Full adder
A B C EXOR SUM
EXOR
Cy
AND
AND
10/28/2013 Digital Logic Version 1.0
OR
6
An N Bit Adder
An Bn Cn-1 A2 B2 C1 A1 B1 C0 A0 B0
FA
Over Flow
C2
FA
FA
C1
HA
C0
Sum n
Sum2
Sum1
Sum0
10/28/2013
The adder-subtracter
A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 A2 B2 A1 B1 A0 B0
Sub
FA S7 Carry
10/28/2013
FA S6
FA
FA
FA
FA
FA S1
FA S0
8
S5 S4 S3 S2 (a) Binary adder-subtractor

Assignment
Q.Design a seven segment LED display
Date of Submission : Tomorrow
10/28/2013
Comparator
To compare relative magnitude of two binary numbers Assume two bit input A and B Outputs
A > B ( A greater than B) A < B ( A less than B) A = B ( A is equal to B)
10/28/2013
10
Truth-table - 2 Bit comparator

A1
0 0 0 0 0 0 0 0 1
A0
0 0 0 0 1 1 1 1 0
B1
0 0 1 1 0 0 1 1 0 0
B0
0 1 0 1 0 1 0 1 0 1
A>B
0 0 0 0 1
A=B
1 0 0 0 0
A<B
0 1 1 1 0
0
0 0 1 1 0 0 1 1 1 0
1
0 0 0 0 1 0 0 0 0 1
0
0 1 0 0 0 0 0 0 0 0
1
1 1 1 1 1 1
0
0 0 1 1 1 1
1
1 0 0 1 1
0
1 0 1 0 1
10/28/2013
11
A>B
B1B0 A1A0
00 0 0
01 1 0
11
10 1 1
00
1
1
01
11
10
10/28/2013
0
12
A=B
B1B0 A1A0
00
01
11
10
00
1
0
0
1
0
0
0
0
01
11
10
10/28/2013
1
13
A<B
B1B0 A1A0
00
01
11
10
00
0
1
0
0
0
0
0
0
01
11
10
10/28/2013
0
14
Comparator- circuit Diagram

A> B = A0 B`1 B`0 + A1A0 B`0 + A1 B`1 A = B = (A0 B`0) (A`1 B1) A<B = A` 1A`0 B0 + A` 0B1 B0 + A`1B1
A0 B`1 B`0 A1 A0 B`0
A1 B`1 A0 B`0 A`1 B1
A>B
10/28/2013
A<B
A=B
15
Assignment
Design a 4-bit magnitude comparator
Date of Submission : Tomorrow
10/28/2013
16
Multiplexers
Data selectors Muxes are widely used in circuits select one input from many
N inputs
MUX
1 Output
M
2 =N M select inputs
2 to 1 Multiplexer
Sel 0 0 0 0 1 1 1 1 A 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 O 0 0 1 1 0 1 0 1
AB
Sel 0 1
00 0 0
01 0 1
11 1 1
10 1 0
10/28/2013
18
2 to 1 MUX. Circuit
O = Sel. A + sel.B A AND
Sel
O B AND
Digital Logic Version 1.0 19
OR
NOT
10/28/2013
Boolean functions of N+1 variables can be N implemented using 2 -to- 1 Multiplexer N of the these variables used as selection lines of the MUX and remaining single variable of the function is used for the inputs of the MUX.Suppose A is this single variable , inputs of the MUX to be chosen to be either A or A`or 0 or 1 In this way ,it is possible to generate any N function of N+1 variables with a 2- to-1 Multiplexer
Boolean-Function Implementation using MUX
Example
Demonstrate this procedure with a example : F(A,B,C) = (1, 3, 5, 6)
Solution:
Assume that ordered sequence of variables chosen for the minterms is ABCD , where A is the leftmost variable in ordered sequence of n variables and BCD . . .are the remaining n-1 variables . 10/28/2013 Digital Logic Version 1.0 21
Procedure
Connect the n-1 variables to the selection lines of the Multiplexer , with B connected to the highorder selection line ,C to the next lower selection lines of Multiplexer and so on down to the last variable , which is connected to the lowest-order selection line s0 .
Digital Logic Version 1.0 22
10/28/2013
Procedure
Consider now the single variable A, since this variable is in the highestorder position in the sequence of variables, it will be complemented in minterms 0 to (2/2) - 1, which comprise the first half in the list of minterms The second half of minterms will have their A variable uncomplemented
Procedure
For a three-variable function, A,B,C we have eight minterms.Variable A is complemented in minterms 0 to 3 and uncomplemented in minterms 4 to 7 List the inputs of MUX and under them list all the minterms in two terms
Procedure
The first row lists all those minterms here A is complemented Second row minterms with A uncomplemented Circle all the minterms of the function and inspect each column separately according the following rules
Rules
If the two minterms in a column are not circled , apply 0 the corresponding Multiplexer input If the two miniterms are circled , apply 1 to the corresponding Multiplexer input
Rules
If the bottom minterm is circled and the top is not circled, apply A to the corresponding Multiplexer input If the top minterm is circled and the bottom is not circled ,apply a` to the corresponding Multiplexer input
Truth table
Minterm
A 0 0 0 0 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0
F 0 1 0 1 0 1 1 0 (c ) Implementation table I0 I1 I2 I3
0 1 2 3 4
A`
A
0
4 0
1
5 1
2
6 A
3
7 A`
5
6 7
1
1 1
1
0 1
(b) Truth table

LOGIC DIAGRAM
1 A A`
4X1 MUX
B C MUX Implementation
Demultiplexers
Logic circuit with one input and many outputs. Can steer the input to one of the output.
N Output signals
1 input signal
DMUX
. . 2=N
M
. . . M control signals
2 to 4 Demultiplexer
Data A Data A B O[0:3] B
1 1 1 1
0 0 1 1
0 1 0 1
1 2 4 8
O[0]
O[1]
O[2]
O[3]
Assignment
Design a 8-to-1 Multiplexer using 2-to-1 Multiplexer
Date of Submission: Tomorrow

Decoder
Multiple outputs and inputs For n inputs and m outputs then m <=2n One of the output will respond to a permissible combination of inputs Also known as minterm recognizer
2 to 4 Decoder
Sel A B
Sl
B O[0:3]
O[0]
1 X 0 0 0 0 0 1 0 1
10/28/2013
X 0 1 0 1
0 1 2 4 8
O[1]
O[2]
O[3]
34
BCD-to-DECIMAL Decoder
Convert binary coded decimal (BCD) to decimal . The input ranges from . Also called 1-of-10 decoder.
10/28/2013
35
BCD-to-DECIMAL Decoder
A B C D
O[0]
O[1]
O[2]
. . .
O[9]
Assignment
Design a 4-to-16 decoder using 3-to-8 decoder
Date of Submission: Tomorrow
10/28/2013
37
Encoder
Generates code based on inputs For an m output code , the input should satisfy 2m >= n Only one input is asserted at a time Priority encoder - each input assigned a priority with respect to other inputs
Decimal-to-BCD Encoder
Convert decimal active input signal to binary coded decimal output signal.
Decimal-to-BCD Encoder
N inputs
. .
.... M outputs
Decimal-to BCD Encoder

+5v
0 1 2 3 4 5 6 7
8 9
A
10/28/2013 Digital Logic Version 1.0
D
40
Priority Encoder
E2 Highest, E1 middle and E0 low E2 encoded as 01, E1 as 10 and E0 as 11 Other conditions 00
E2 0 0 0 0 1 E1 0 0 1 1 d E0 0 1 0 1 d O1 O2 0 1 1 1 0 0 1 0 0 1
Truth Table
10/28/2013
41
Truth Table for priority encoder

E2 E1 E0 0 00 01 11 10
0 1
E2 E1 00
1 1
0 0
0 0
O1 = (E2E1 + E2E0)
E0 0
01
11
10
0 1
10/28/2013
0
0
1
1
1
1
O0 =( E1E0 + E2)
42
Circuit for priority encoder

E0 E1 E2
O1
O2
10/28/2013
43
Assignment
Design a 4-bit priority encoder

Date of Submission :
TOMMOROW
PARITY
Even parity: N-bit input has an even
numbers of 1s.
Odd parity : N-bit input has an odd

numbers of 1s. Ex:11111 0000 1111 0011 even parity 11111 0000 1111 0111 Odd parity Ex-OR GATE : Has a high output when parity is odd. Has a low output when parity is even.
PARITY GENERATOR
An extra bit that is generated and attached to a binary number is known as parity generation. The logic circuit responsible for the generation is known as parity generator.
PARITY CHECKERS
The logic circuit which checks binary bits at the receiving end is parity checker. Exclusive-OR gates are ideal for generating and checking the parity of a binary number.
Odd-parity Generation
X7 X6 X5 X4 X3 X2 X1X0
( Instruction or data bits) X8 9-bit number with odd parity

Practical Application
Because of transients,noise and other disturbances, 1-bit errors can occur when binary data is transmitted. Parity generator at the transmitting and parity checker at the receiving end can be used to check 1-bit errors. Parity generator and checker can be odd or even .
Example
You want to send 0100 0011 Enter the data to a odd parity generator The data to be transmitted will be 0 0100 0011 Send the data 0 0100 0011 to some destination. If no errors occur in transmission , the odd-parity checker at the receiving end will produce a high output Means the received number has odd parity

Comb Cir

Загружено:

Сведения о документе

Оригинальное название

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

Comb Cir

Загружено:

Авторское право:

Доступные форматы

Combinational Circuits

Digital Logic Version 1.0

Arithmetic circuit- Half adder

1 = AB` 0 SUM + A`B 1 0

Half Adder Circuit

Karnaugh Map ...

Digital Logic Version 1.0

S5 S4 S3 S2 (a) Binary adder-subtractor

Date of Submission : Tomorrow

Digital Logic Version 1.0

Digital Logic Version 1.0

Truth-table - 2 Bit comparator

Digital Logic Version 1.0

Digital Logic Version 1.0

Digital Logic Version 1.0

Digital Logic Version 1.0

Comparator- circuit Diagram

Date of Submission : Tomorrow

Digital Logic Version 1.0

Digital Logic Version 1.0

Boolean-Function Implementation using MUX

(b) Truth table

Date of Submission: Tomorrow

Digital Logic Version 1.0

Date of Submission: Tomorrow

Digital Logic Version 1.0

Decimal-to BCD Encoder

Digital Logic Version 1.0

Truth Table for priority encoder

Digital Logic Version 1.0

Circuit for priority encoder

Digital Logic Version 1.0

Design a 4-bit priority encoder

Odd parity : N-bit input has an odd

( Instruction or data bits) X8 9-bit number with odd parity

Вам также может понравиться