Part I: Periodic Interrupt Timer, MPC555 Interrupt Systems

Periodic Interrupt Timer

Timer has many uses
To implement a clock To check user input periodically To monitor environment changes To switch between programs

Periodic Interrupt Timer How does a timer work?

count reset clock -1 Adder mux count register zero? timer expires

A timer is basically a counter of clock cycles.

Periodic Interrupt Timer

Time Period = (count + 1) clock cycle time = (count + 1) / clock frequency
EX: The clock frequency is 5MHz. The needed time period is 10ms. What is the count value?

Periodic Interrupt Timer

EX: The clock frequency is 5MHz. The needed time period is 1 second. The count register is 16-bit.
What is the count value, and how to make it work?

Periodic Interrupt Timer

How to program a timer?
Set up count value Check if the timer expires Configure interrupt, if interrupt is to be used Read leftover value, if the can be supported

MPC555 PIT Programming

PTE PITC Clock Disable 16-bit Modulus counter PS PIT Interrupt PIE

PIF

PTE: PIT enable PITC: PIT count value PIE: PIT interrupt enable

PIF: PIT freeze PS: PIT status PITR: leftover value in the counter
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MPC555 PIT Programming

MPC555 PIT programming interface
1.

PISCR: Periodic Interrupt Status & Control Register

2.
3.

PITC: PIT Counter

PITR: Periodic Interrupt Timer Register

PISCR: Periodic Status & Control Register MPC555 PIT Interrupt Programming
0x002FC240
Interrupt level for PIT 1 2 3 PIRQ PS PIE 13 PITF 14 PTE 15 4 PInterrupt Enable 0: disable interrupt 1: enable interrupt 5 6 7

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PIT Status 0: no PIT int asserted 1: PIT int asserted

PIT Freeze 0: no effect 1: disable decrement counter if internal signal FREEZE is asserted

PIT Enable 0: disable decrement counter 1: enable decrement counter

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PITC: PIT Counter

0x2F C244
0 16

PITC

PITC: PIT counter

PIT Time-out period = (PITC+1)/(PIT Frequency); assume 1MHZ oscillator PIT Period = 1/(1MHz) = 1 microsecond Put 33000 in PITC to get 33 milliseconds interrupt period.
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PITR: Periodic Interrupt Timer Register

If you want to read the current PIT count to estimate time to next PIT interrupt?

0x2F C248
0 15 16 31

PIT

Reserved

PIT: Leftover (current) count in PIT counter Writes to PITR have no effect: read only.
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PIT Initialization .equ USIU_BASE_UPPER 0x2f

.equ PICSR_OFFSET 0xc240 .equ PITC_OFFSET 0xc244 .equ PITR_OFFSET 0xc248 ; r4 base address of SIU regs lis r4, USIU_BASE_UPPER ; set PICSR bits: PIRQ=08, PS=PS, PIE=1, PITF=0, PTE=0 ; so OS flag is cleared, interrupt is enabled, timer is ; enabled, interrupt level is assigned, and device disabled li r0,0x0800 sth r0,PICSR_OFFSET(r4) ;PITC = 33000 = 0x80e8 and store it in PITC li r5, 0x80e8 sth r5, PITC_OFFSET(r4) ;now enable PIT: PTE = 1 lhz r0, PICSR_OFFET(r4) ori r0, r0, 0x1 sth r0, PICSR_OFFSET(r4)

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MPC555 Exception Processing

device 1 device 2 device n External Interrupts Interrupt controller External interrupt exception CPU

Other ESR

External Interrupt ESR ISR 1 ISR 2

Other ESR

ISR n
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MPC555 Exception Processing

General Procedure of External Interrupt ESR 1. Save machine context 2. Make execution recoverable and enable external interrupt 3. Save user registers 4. Determine interrupt source 5. Branch to ISR 6. Restore user register contents 7. Restore machine context 8. Return to program execution
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MPC555 Exception Processing

What registers should be saved by CPU upon an exception?
Should all registers be saved ALWAYS? Modern processors: Software saves almost all registers

But who should save the PC, CPU or software?

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MPC555 Exception Processing

Another register: MSR (Machine State Register)
User and supervisor modes: An ESR runs in the supervisor mode:
Corresponding to the administrator privilege
May access and change protected registers and memory

areas

How does the CPU switch to the supervisor mode?

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MPC555 Exception Processing

Machine State Register (MSR)
0
EEPR PR=0: supervisor =1: user EE=ext. interrupt enable =0: disable =1:enable RI=1: recoverable 0 IP IR DR 0 0 RI LE IP=0: exception Vector table LE=0 Starts at Big-endian 0x000 else 0xfff

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MPC555 Exception Processing

Upon an exception, the CPU
1. 2.

Puts the ESR address into PC (forces a jump to the ESR) Change MSR bits PR 0: Switches to supervisor mode (0: supervisor, 1: user) EE 0: Disables further external interrupts RI 0: Indicates not recoverable

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MPC555 Exception Processing

Key point: ALL register values, if changed, must be saved and restored

Include r0-r31, CR, LR, XER, PC, MSR and others

ESR should save those register contents

Can use stack But the CPU has changed the contents of PC and MSR!

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MPC555 Exception Processing

SRR0/SRR1: To save PC and MSR
Solution: Use special registers to help save them SRRx: Machine status Save/Restore Registers SRR0 saves PC, SRR1 saves the changed bits in MSR How it works:
1. 2.

The CPU saves PC to SRR0, MSR to SRR1* The ESR saves SRR0/SRR1 into stack

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MPC555 Exception Processing

Programming methods for saving SRR0/SRR1: Example:
mfspr srr0, r3 stw r3, 24(sp) lwz r3, 24(sp) mtspr srr0, r3 ; copy srr0 to r3 ; save srr0 value ; get srr0 value in r3 ; copy it to srr0

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Nested Interrupts
If the interrupt ESR or an ISR is running, can the CPU accept another interrupt?
Is it desirable to accept another interrupt? When cannot the CPU accept another exception?

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Nested Interrupts
EE bit: Tell the CPU not to accept another interrupt

External interrupt Enable bit Reset to zero: The external interrupt exception is ignored; the CPU keeps running

The CPU automatically resets the EE bit upon an exception But the ESR may re-enable the EE bit

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Recoverable Exceptions
Other exceptions may happen during an interrupt processing Scenario: Stack overflow during the interrupt processing
Interrupt processing is not always recoverable Scenario: The stack overflow happens before saving SRR0/SRR1 Solution: Use the RI bit

The CPU automatically resets the RI bit The ESR may re-enable it
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