CMOS Circuit Design:

Challenges of Nano Electronics

Susanta Sen
Institute of Radio Physics and Electronics
University of Calcutta

08/09/09 NERIST 2009 1

 Review of

MOS Transistor

08/09/09 NERIST 2009 2

 The MOS Transistor

08/09/09 NERIST 2009 3

 MOS Transistor

Depletion Inversion

08/09/09 NERIST 2009 4

 MOS Transistor (contd.)

ID VG

Vt
VDS
Channel Pinches off → Current Saturates

Saturation Current increases with VG

Threshold Voltage Vt → Device Turns ON

MOS can be used as SWITCH

08/09/09 NERIST 2009 5

 MOS as SWITCH
Designing Logic Circuits
Logic ‘0’ = 0V : Logic ‘1’ = VDD

n-MOS : VG ≤ Vt → OFF : VG = VDD → ON

p-MOS : VG ≥ VDD– Vt → OFF : VG = 0 → ON

Gate Voltage → Negative w.r.t. Channel
08/09/09 NERIST 2009 6
 n-MOS SWITCH
Transferring Logic ‘1’ (VDD): Transistor
OFF
Vin = VDD VDD Vt
Source
Impedance
Vo High
VDD
Weak ‘1’
t
Transferring Logic ‘0’ (0 V):
VDD
Source
Transistor
Vin = 0 V Impedance
Vo ON
Low

VDD Strong ‘0’

t

08/09/09 NERIST 2009 7

 p – MOS Switch
Transferring Logic ‘1’ (VDD):

VDD VDD Strong ‘1’

Vo
0V

t
Transferring Logic ‘0’ (0 V):
0V VDD

Vo
Weak ‘0’
0V Vt
t
08/09/09 NERIST 2009 8
 CMOS Logic
• Use n-MOS to produce Logic ‘0’ → Pull DOWN
• Use p-MOS to produce Logic ‘1’ → Pull UP

The CMOS Inverter

Equivalent Logic ‘1’ Logic ‘0’

Circuit Output Output

08/09/09 NERIST 2009 9

 Review of Switching Theory
Switches in Series

C F = C and (A and B)

A B

Switches in Parallel
A

C F = C and (A or B)

B
08/09/09 NERIST 2009 10
 Using n-MOS Switch
Constraint : C = ‘0’
Series Connection
C = ‘0’ F = ‘0’ and (A . B) = A nand B

A B

Parallel Connection
A

C = ‘0’ F = ‘0’ and (A or B) = A nor B

08/09/09 NERIST 2009 11

 Using p-MOS Switch
Constraint : C = ‘1’
Series Connection
C = ‘1’ F = ‘1’ and ( A . B) = A + B

A B
Parallel Connection
A

C = ‘1’ F = ‘1’ and ( A + B) = A . B

08/09/09 NERIST 2009 12

 CMOS Logic Design
• Pull UP Network
– Build using p-MOS
– Turns ON when Function is TRUE
• Pull DOWN Network
– Build using n-MOS
– Turns ON when Function is FALSE
• Operationally Complement
• Topologically Dual
08/09/09 NERIST 2009 13
 CMOS Logic (contd.)

A A B

B
F
F
A

A B
B

NOR Gate NAND Gate

08/09/09 NERIST 2009 14

 CMOS Design Example
Consider the Function
f = A . (B + C) B
A
f = ‘0’. [A . (B + C)] C

Pull Up
F
B C

A
Design the
Pull Down
Network

08/09/09 NERIST 2009 15

 CMOS Design Example
Consider the Function
f = A . (B + C)
B
The Pull Down Network connects
A
‘f ’ to ground when
C

Pull Up
f = [A . (B + C)] is true F
B C

A
Design the
Pull Down
Connect Ground
Network first

08/09/09 NERIST 2009 16

 Power Dissipation
• No Static Dissipation
– Except leakage current
• Dynamic Dissipation
– Charging and discharging load capacitor
• Direct Path Dissipation
– During switching

08/09/09 NERIST 2009 17

 Dynamic Dissipation (0 → 1)
IL= CL.dVo/dt

IL
Edrawn= VDD∫ILdt = VDDCL∫dVo = CLVDD2
Vo

Ediss(in Rp) = ∫(VDD- Vo) ILdt

= CL∫(VDD- Vo)dVo = ½CLVDD2

P-MOS On
N-MOS
∴ Estored (in CL)= ½CLVDD2
08/09/09 Off NERIST 2009 18
 Dynamic Dissipation (1 → 0)

Ediss(in Rn) = Estored= ½CLVDD2

Vo

08/09/09 NERIST 2009 19

 CMOS Logic Circuit
Advantages
• Low Power Dissipation in Steady State
– Either Pull-up OR Pull-down ON
– No direct path current from VDD → Gnd
– No (negligible) Steady State Dissipation

• High Packing Density

– Large Circuits on single chip → billion devices
– Significant Static Dissipation
08/09/09 NERIST 2009 20
 MOS Amplifier
VO = VDD – ID.RL Load Line

ID
V VG
DD
ID
RL V VDS
VDD DD
VO
Vi
VO
(=VG)

Vi

08/09/09 NERIST 2009 21

 Non Linear Load
VO= VDD – Vdiode LOAD LINE

VDD
ID

VDD VDS
VO
VDD
Vi

VO

Vi

08/09/09 NERIST 2009 22

 Non Linear Load (contd.)
VDD

ID
VB
VO
Vi
VDS
VDD
VDD

VO

Vi

08/09/09 NERIST 2009 23

 Amplifier
The CMOS or Inverter
Inverter?

ID

Vi VO VDDVDS
VDD

VO
Gate Bias of PMOS changes with
Input Voltage
Vi VDD

08/09/09 NERIST 2009 24

 A Closer Look
VO= f (Vi) → Gain = ∂VO/∂
VOH
Vi presence of Noise
In
VO = f (Vi + vn)
VO = f (Vi) + vn(∂VO/∂Vi) + vn2(∂ 2VO/∂Vi2)+…
noisy_output = noiseless_output +
noise x gain + higher order terms

VOL

ViL ViH
Vi

Digital → Noise immunity Analog → High Gain

08/09/09 NERIST 2009 25
 The Amplifier : A Closer Look
Slope = - 1/RL
VO = VDD – ID.RL
V
DD
VG

RL iO ID+ id
Q id = gmvi

Vi + vi VO+ vo

VDS
VQ VDD

Gain = vo/vi = - gm RL
vo = - gmvi RL

08/09/09 NERIST 2009 26

 Small vs Large Signal
Where is the Q-point
Large Signal limits
• Cut off & Saturation
• Q-point
VO
 Middle of range
• Signal will be distorted
 Specify limits
Small Signal Q-point Vi
• Maximum gain
• Linear region
• Minimize Distortion
08/09/09 NERIST 2009 27
A Closer Look at the Characteristics
Gain = – gm R
RLL||rO

ID

VDS

ID = (k'/2) (W/L) (VGS – VT)2 (1 + λVDS)

λ = ∆ L/(LVDS) → Channel Length Modulation Coefficient

08/09/09 NERIST 2009 28

 The Analytical Approach
∂ID ∂ID
dID = dVG + dVD
∂VG ∂VD
ID
∂ID
v = gm → Transconductance
VD ∂VG
vi V o ∂ID
G
= go → O/P Conductance
∂VD
The current source load keeps drain current const. So,
dID = 0 = gm.vi + go.vo
Hence, Voltage Gain (Ao) is

Ao = vo / vi = – gm / go = gm ro
08/09/09 NERIST 2009 29
 The Equivalent Circuit
D • The 3 terminals
• Current source dependent on
G input voltage → (gmvGS)
• Current source dependent on its
S on
terminal voltage→→rOg=Ov1/g
outputvoltage DS O
G D

gmvGS rgOO=vDS
1/gO

S
08/09/09 NERIST 2009 30
The Transistor Parameters: gm & go
In saturation
ID = (k'/2)(W/L)(VG – VT)2
where, k' = µ Cox and VT = VT0 – αVsb ,
VT0 is the threshold voltage without substrate bias and
α is the parameter that accounts for the effect of
substrate bias Vsb.
2
Let VG – VT = VGT → ID = (k'/2)(W/L) VGT

gm = (∂ID/∂VG) = k'(W/L) VGT

08/09/09 NERIST 2009 31
 Transconductance (contd.)
Three Formulae (!!!)
gm = k' (W/L)VGT Is gm linearly dependent on
Transistor size ?
But
√
2ID Or dependent on its
VGT = k'(W/L) square root ?
Or independent of (W/L) ?
∴gm = √2k'(W/L)ID
To increase gm
Shall we increase VGT ?
2
Also, k'(W/L) = 2ID/VGT
Or decrease it ?
∴gm = 2ID/VGT
08/09/09 NERIST 2009 32
 Which Formula ?
Depends on how the Transistor is
BIASED and SIZED
If Size and VGT are known → Use the first one

If Drain Current and Size are known → Use the

second

If the Drain Current and Gate Voltage are given

and the Transistor is accordingly sized → Use
the third
08/09/09 NERIST 2009 33
 Output Resistance (ro)
2
ID = (k'/2)(W/L)VGT (1 + λVDS)

∴ gO = (∂ID/∂VDS) ≈ λ ID = λ' ID /L
Defining, λ' = λL = (∆L/VDS)
→ A technology dependent
parameter
Also, at VDS = – 1/λ = – VA → ID = 0
VA → Early voltage
gO = ID /VA

08/09/09 NERIST 2009 34

 Amplifier Gain
In terms of Geometry and VGT

AO = – (2L/λ' VGT)

In terms of Drain Current and Geometry

AO = (1/λ') √2k‘(W L)/ID

Thus if the Transistor is biased at a constant current,

the DC Gain is determined by the square root of the
Gate Area.

08/09/09 NERIST 2009 35

 The AC Behaviour
vi Cgd vO
G D
Cg gmvi rO CO

sCgd(vi – vO) – gmvi – (vO/rO) – sCOvO = 0

vi (sCgd – gm) – vO (sCgd + 1/rO + sCO) = 0

So the AC Gain
1 – sCgd / gm
A1 = vO/vi = – gm rO
1 + srO (Cgd + CO)
08/09/09 NERIST 2009 36
 Bandwidth
1 – sCgd / gm
A1 = – gm rO
1 + srO (Cgd + CO)

Let Ctot = Cgd + CO

1 – sCgd / gm
Then , A1 = – gm rO
1 + srO Ctot
Normally, ω Cgd/gm << 1

Therefore, A1 ≈ AO/(1 + srO Ctot)

This describes the frequency response of a system
with one dominant pole
The bandwidth is given by 1/ rO Ctot
08/09/09 NERIST 2009 37
 Gain Bandwidth Product
AO
(AO – 3 dB)

Gain (dB)

BW GBW
Frequency

GBW = (gm rO)/(rOCtot) = gm /Ctot

The Gain-Bandwidth product (or the cutoff frequency)

is independent of rO
08/09/09 NERIST 2009 38
 The Current Source
VDD
ID1 = (k'/2)(W/L)1(VGS – VT)2
Iref R IO
ID1 = Iref = (VDD – VGS)/R

Q1 Q2

IO = ID2 = (k'/2)(W/L)2(VGS – VT)2

IO (W/L)2
Iref = (W/L)1

08/09/09 NERIST 2009 39

 Current Steering

Q5 Q4

Iref IO
I2 I1

Q1 Q2
Q3

08/09/09 NERIST 2009 40

 Attention to Speed / BW
Delay → Req.CL
Req → Transistor (W/L) ratio
•p-MOS slower than n-MOS
 Hole mobility < Electron mobility
 Pull-UP → Higher Resistance
 Rise time longer

• Make p-MOS wider

 Resistance α W/L Ratio
 Wp = 2. Wn

CL → Transistor Area (W.L)

08/09/09 NERIST 2009 41
 SCALING
• Reduce Transistor Dimensions (W and L)
by a factor ‘s’
 Req unaltered → W/L
 CL reduced by factor s2
• Improves Speed
• Reduces Dissipation per Signal Transition
Reduce device size → Towards nano-MOS
08/09/09 NERIST 2009 42
 CHALLENGES OF SCALING
• Device Technology
 Fabrication → Lithography, Etching
 New Device Configuration

• Material Limitations → Thin Oxides

 Gate Oxide → Large Leakage
 High-k dielectric
 Inter-layer → Large parasitic capacitance
 Low-k dielectric
08/09/09 NERIST 2009 43
 CHALLENGES OF SCALING

• Interconnect Technology
 Line delay limits circuit speed
 Optical interconnect → Silicon Photonics

• Device Physics
 Quantum Size Effect
 Ballistic Transport
 Develop New Models

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