Presents by

S.Rajeswari PG Scholar M.E VLSI Design Under Guidance of

Mr.R.Ponnangan AP/ECE

Abstract
Detection and decoding performs sequentially
Soft error detection(Logical Errors) The corrected code has been produced as an output

Existing System
Majority Logic decoder
Correction depends on parity check equations Induced bit-flips to the Low-Density Parity Check codes

After the Nth cycle the result has been produced

Proposed System
Majority Logic detector/decoder
Different set cyclic codes Part of Low-Density Parity Check codes

The Majority Logic Detection/Decoding process has been done in 3 cycles

Control unit manages the detection process

Flow Chart

LITERATURE SURVEY
Sl.no TITLE TECHNOLOGY ITERATION AREA SPEED CODE CORRECTION 1 EFFICIENT MAJORITY LOGICAL FAULT DETECTION WITH DIFFERENCE SET CODES FOR MEMORY APPLICATIONS MAJORITY LOGICAL FAULT DETECTION NO NO NO YES 2 RADIATION INDUCED SOFT ERRORS IN ADVANCED SEMICONDUCTOR TECHNOLOGY SOFT ERROR RATE NO YES YES YES

MODELS AND ALGORITHMIC LIMITS FOR AN ECC-BASED APPROACH TO HARDENING SUB-100-nm SRAMs

BIT ERROR RATE

NO

YES

NO

NO

DEC ECC DESIGN TO IMPROVE MEMORY RELIABILITY IN SUB-100nm TECHNOLOGIES

DOUBLE ERROR CORRECTION

NO

YES

YES

NO

DIFFERENCE-SET CYCLIC CODES

MAJORITY LOGIC DECODER

YES

NO

NO

YES

IMPLEMENTATION OF CORRECTED CODE BY IMPROVING THE SPEED OF DETECTION AND DECODING PROCESS

MAJORITY LOGIC DETECTION AND DECODING

YES

YES

YES

YES

Block Diagram
WORD

ENCODER MEMORY

N CYCLE PROCESS

PLAIN ML DECODER WORD

SYNDROME FAULT DETECTOR

MAJORITY LOGIC DETECTOR/ DECODER

3 CYCLE PROCESS

Modules
Error detection upto N cycle
Plain ML decoder Syndrome fault detector

Majority logic detector/decoder

Detection and decoding in 3 cycles

Reference
R. C. Baumann, Radiation-induced soft errors in advanced semiconductor

technologies, IEEE Trans. Device Mater. Reliabil., vol. 5, no.3, pp. 301316, Sep. 2005 J. von Neumann, Probabilistic logics and synthesis of reliable organisms from unreliable components, Automata Studies, pp. 4398, 1956. M. A. Bajura et al., Models and algorithmic limits for an ECC-based approach to hardening sub-100-nm SRAMs, IEEE Trans. Nucl. Sci.,vol. 54, no. 4, pp. 935945, Aug. 2007. R. Naseer and J. Draper, DEC ECC design to improve memory reliability in sub-100 nm technologies, in Proc. IEEE ICECS, 2008, pp.586589.

Cont..
S. Ghosh and P. D. Lincoln, Low-density parity check codes for errorcorrection in

nanoscale memory, SRI Comput. Sci. Lab. Tech. Rep.CSL-0703, 2007 H. Naeimi and A. DeHon, Fault secure encoder and decoder for NanoMemory applications, IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol. 17, no. 4, pp. 473486, Apr. 2009 E. J.Weldon, Jr., Difference-set cyclic codes, Bell Syst. Tech. J., vol.45, pp. 1045 1055, 1966. T. Shibuya and K. Sakaniwa, Construction of cyclic codes suitable for iterative decoding via generating idempotents, IEICE Trans. Fundamentals,vol. E86-A, no. 4, pp. 928939, 2003.

Cont
Shih-Fu Liu, Pedro Reviriego, Efficient Majority Logic Fault Detection With

Difference-Set Codes for Memory Applications, IEEE Transactions On Very Large Scale Integration (Vlsi) Systems, Vol. 20, No. 1, January 2012