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Learning Objectives
Understand the basic elements of an instruction cycle and the role of interrupts. Describe the concept of interconnection within a computer system Understand the difference between synchronous and asynchronous bus timing Present an overview of PCI
Computer Components
Hardwired Program hardware program constructed by connecting various logic components to store binary data and perform arithmetic and logical operations Concept of Hardwired Program
Hardwired systems are inflexible General purpose hardware can do different tasks, given correct control signals Instead of re-wiring, programmer supplies a new set of control signals
Computer Components
What is a program?
A sequence of steps For each step, an arithmetic or logical operation done For each operation, a different set of control signals is needed
Data
Results
Programming in Hardware
Computer Components
Software Program
With the general-purpose hardware, there is no need to rewire the hardware but only to provide a new sequence of codes Software a sequence of codes/instructions Instruction codes Data Instruction interpreter
CPU
Control signals General Purpose Arithmetic and Logic Functions Programming in Software Results
Components of Computer
The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit Data and instructions need to get into the system and results out
Input/output
Program Execution
To store the address in memory for the next read or write To store data to be written/receives from the memory Specifies a particular I/O device Exchange data between I/O module & CPU
Computer Function
Basic Function of Computer executes program (a set
of instructions stored in the memory) done by the processor
Two steps for instruction processing: 1. Fetch processor reads (fetches) the instructions
from memory one at a time 2. Execute processor executes each instruction
Computer Function
Fetch Cycle Program Counter (PC) holds address of next instruction to fetch Processor fetches instruction from memory location pointed to by PC Increment PC
Unless told otherwise
Instruction loaded into Instruction Register (IR) Processor interprets instruction and performs required actions
Computer Function
Processor I/O
Data transfer between CPU and I/O module
Data processing
Some arithmetic or logical operation on data
Control
Alteration of sequence of operations e.g. jump
Combination of above
Computer Function
15
Opcode
Address
Instruction Format 4 bits 24 = 16 different opcodes, 212 = 4096 (4K) words of memory (address)
15
Magnitude
Integer Format Program counter (PC) = Address of instruction Instruction register (IR) = Instruction being executed Accumulator (AC) = Temporary storage 0001 = Load AC from memory 0010 = Store AC to memory 0101 = Add to AC from memory
Add the content of 940 and 941 and store results in 941 (3 fetch + 3 execute cycles = 3 instruction cycles)
PC contains address of 1st instruction (300) Loaded into IR and the PC is incremented Process involves the use of MAR and MBR (but ignored)
The first 4 bits in the IR indicate that the AC is to be loaded The remain 12 bits specify the address (940) from which data is to be loaded into AC
Old contents of the AC and the contents of 941 are added Result is stored in the AC
if
of
os
iod
do
iac
oac
oac
c. operation decoding (iod) analyze d. e. f. Data operation address fetch (of) (do) calculation fetch perform the (oac) operand the operation determine from in memory/read the address of g. Operand store (os) write result into memory or via I/O a. Instruction b. Instruction fetch address (if) calculation read instruction (iac) determine from its memory the instruction and determine ofexecuted operation and type of the from instruction operand I/O of address location into next the instruction processortype to be operand(s) to be used
Interrupts
Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing Provided to improve processing efficiency Classes of Interrupts Program
e.g. overflow, division by zero
Timer
Generated by internal processor timer Used in pre-emptive multi-tasking
I/O
Generated from I/O controller (to signal completion/error)
Hardware failure
e.g. memory parity error/power failure
Interrupt Cycle
Added to instruction cycle Processor checks for interrupt
Indicated by an interrupt signal
Interrupts: an interruption of the normal sequence of execution execution resumes when interrupts processing is completed
Interrupt cycle processor checks to see if any interrupts have occurred, indicated by the presence of an interrupt signal. No interrupt processor proceeds to the fetch cycles and fetched the next instruction
The time required for the I/O operation is relatively short; less than the time to complete the execution of instructions between write operations in the user program
A gain in efficiency because part of the time during which I/O operation is underway overlaps with the execution of user instructions
Multiple Interrupts
Disable interrupts
Processor will ignore further interrupts whilst processing one interrupt Interrupts remain pending and are checked after first interrupt has been processed Interrupts handled in sequence as they occur
Define priorities
Low priority interrupts can be interrupted by higher priority interrupts When higher priority interrupt has been processed, processor returns to previous interrupt
Interrupts are handled in strict sequential order Drawbacks does not take into account relative priority or time-critical needs
Defines priorities for interrupts and to allow an interrupt of higher priority to cause a lower-priority interrupt handler to be itself interrupted
begins
Printer interrupt occurs; info is placed on the system stack and execution continues at the printer ISR communication ISR is completed, the printer ISR is executed. But, higher-priority disk interrupt and control transfers to the disk ISR
only when routine is completed, printer ISR is resumed, and finally return to the user
Interconnection
All the units must be connected Different type of connection for different type of unit
Memory Input/Output CPU
Computer Modules
Types of exchanges that are needed by indicating the major forms of input and output
Computer Modules
Types of exchanges that are needed by indicating the major forms of input and output
Computer Modules
Types of exchanges that are needed by indicating the major forms of input and output
Read data and instructions and writes our data; Receives and acts on interrupts; Control signal to control operation of the system
Memory Connection
Receives and sends data Receives addresses (of locations) Receives control signals
Read Write Timing
Input/Output Connection(1)
Similar to memory from computers viewpoint Output
Receive data from computer Send data to peripheral
Input
Receive data from peripheral Send data to computer
Input/Output Connection(2)
Receive control signals from computer Send control signals to peripherals
e.g. spin disk
CPU Connection
Reads instruction and data Writes out data (after processing) Sends control signals to other units Receives (& acts on) interrupts
Buses Interconnection
There are a number of possible interconnection systems Single and multiple BUS structures are most common e.g. Control/Address/Data bus (PC) e.g. Unibus (DEC-PDP)
What is a Bus?
A communication pathway connecting two or more devices Usually broadcast Often grouped
A number of channels in one bus e.g. 32 bit data bus is 32 separate single bit channels
Data Bus
Carries data
Remember that there is no difference between data and instruction at this level
Address bus
Identify the source or destination of data e.g. CPU needs to read an instruction (data) from a given location in memory Bus width determines maximum memory capacity of system
e.g. 8080 has 16 bit address bus giving 64k address space
Control Bus
Control and timing information
Memory read/write signal Interrupt request Clock signals
Path for moving data To designate the source between system or destination of the module data on the data bus
To control the access to and the use of the data and address lines
Sets of wires
Expansion Bus buffers data transfer between the system bus and the I/O controllers
High-Speed Bus to compensates for loss of performance when higher performance I/O devices are attached to the expansion bus
Multiplexed
Shared lines Address valid or data valid control line Advantage - fewer lines Disadvantages
More complex control Ultimate performance
Distributed
each module may claim the bus Control logic access on all modules
Processor places a memory address on the address line + various status line
Once address line have stabilized, processor issues an address enable signal
Memory recognizes the address & places data on the data line READ operation: Processor issues a read command
WRITE operation: Processor puts the data on the data lines & issues a write command after data lines have a Memory copies the info from data lines during the 3 rd clock cycle stabilized
Once the processor has read the data, it de-asserts (stops) the read signals
Memory decodes the address & places the data on the data line
Once data lines have stabilized, memory module asserts (inform) the acknowledged line that data is available Causes memory to drop the data & acknowledge lines Acknowledge line is dropped, master (processor) removes the address info
Master drops the WRITE signal and memory module drops the acknowledge signal
Memory module responds to the WRITE command by copying the data from the data lines and then asserting the acknowledge line
PCI Bus
Peripheral Component Interconnection Intel released to public domain High bandwidth, processor independent bus that functions as a peripheral bus Gives better performance for high-speed I/O subsystems (network interface controllers/graphic display adapters) Current standard allows 64 data lines Economical and needs very few chips to implement May be configured as a 32- or 64-bit bus
Error lines
JTAG/Boundary Scan
For testing procedures
PCI Commands
Transaction between initiator (master) and target Master claims bus Determine type of transaction
e.g. I/O read/write