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SIMATIC S7
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Objectives
- Review On The Logic Gates & How It Is represented In LAD, STL, FBD - Know The Set-Reset Functions.
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OR Gate
S3 (I 0.2)
AND Gate
S1 (I 0.0)
S4 (I 0.3)
Circuit Diagram
S2 (I 0.1)
L3 (Q 8.2)
L2 (Q 8.1)
I 0.2
I 0.3
Q 8.0
Q 8.1
LAD Diagram
I 0.2 I 0.3
>=1
Q 8.2 =
I 0.0
&
FBD Diagram
I 0.1
Q 8.0 = Q 8.1 =
O O =
SIMATIC S7
STL
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A A = =
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XNOR Gate
S1 (I 0.6) S2 (I 0.7) S1 (I 0.6) S2 (I 0.7)
XOR Gate
Circuit Diagram
S1 (I 0.4) S2 (I 0.5)
S2 (I 0.5) S1 (I 0.4)
L1 (Q 8.0)
Q 8.0
LAD Diagram
I 0.6 I 0.7
I 0.4
I 0.5
Q 8.0
I 0.4
I 0.5
Q 8.0 =
FBD Diagram
STL
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Example:
1- Convert the Following Circuit Diagram to LAD. 2- Convert the LAD Diagram to STL.
I0.2 I0.4 I0.0 I0.1 I0.3 I0.5 I1.0
Answer:
1I0.6
I0.7
Q0.0
2-
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SIEMENS
Exercise:
1- Convert the Following Circuit Diagram to STL.
I0.0 I0.2 I0.5 I0.7 I1.3 I0.1 I0.3 I0.6 I1.0 I1.5 I1.2 I1.4
I0.4 I1.1
I1.7
I1.6
Q0.0
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Set
The specified address is set to signal state "1" and remains set until another instruction resets the address.
Reset
The specified address is reset to signal state "0" and remains in this state until another instruction sets the address again.
I 0.0
I 0.1
I 0.2
Q 0.0
Q 0.0
(S)
LAD Diagram
I 0.3
(R)
I 0.0 I 0.1
FBD Diagram
>=1
Q 0.1 R
I 0.3
STL
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Setting/Reseting FlipFlop
Dominant Set M1.0 R I 0.5 S M1.0 I 0.4 R RS Q0.2 I 0.5 S A R A S A =
SIMATIC S7
SIEMENS LTD EGYPT 2007 All Rights Reserved
Setting/Reseting FlipFlop
Dominant Reset M1.1
I 0.4
RS
Q 0.2
I 0.4
SR
Q 0.3 Q
LAD Diagram
I 0.5
R
M1.1 I 0.4 S R A S A R A = I 0.4 M 1.1 I 0.5 M 1.1 M 1.1 Q 0.3
November 21, 2013
SR Q0.3
FBD Diagram
I 0.5 Q
STL
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I 0.3
I 0.4 NOT
M 1.0 Q 0.3
LAD Diagram
( )
( )
( )
I 0.0
& M0.6
I 0.1
&
I 0.3 I 0.4 M1.0 Q 0.3 =
FBD Diagram
STL
A A = A A A NOT = A = 9/8
I I M M I I M M Q
0.0 0.1 0.6 0.6 0.3 0.4 1.0 1.0 0.3 November 21, 2013
SIMATIC S7
SIEMENS LTD EGYPT 2007 All Rights Reserved
SIEMENS
SET
The SET instruction sets the RLO to "1" without preconditions
CLR
The CLEAR instruction sets the RLO to "0" without pre-conditions
NOT
The NOT instruction inverts the RLO.
NOt EXIST
LAD
NOt EXIST
LAD
I 0.0
I 0.1
Q0.0
NOT
( )
&
FBD
NOt EXIST
FBD
I 0.1
Q0.0 =
SET = M 0.4
STL
CLR = M 0.5
STL
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I 1.0 I 1.1
M1.0 N
M0.2
I 0.0 I 0.1
M0.0 P
M0.1
LAD Diagram
I 1.0
I 1.0 I 1.1
&
M1.1
M0.2
&
M1.0
M0.1
FBD Diagram
I 1.1
A A FN =
STL
A A FP =
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Positive Edge
(Positive Edge Detection) detects a signal change in the address (M0.1) from "0" to "1", and displays it as RLO = "1" after the instruction.
Examples 1:
OB1-Cycle
I 0.0 I 0.1
RLO
Negative Edge
(Negative Edge Detection) detects a signal change in the address (M1.1) from "1" to "0" and displays it as RLO = "1" after the instruction (such as at M 0.1) for one cycle.
M8.0 M8.1
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Unconditional Jump
In LAD/FBD, the label (M001) is entered as an identifier above the coil symbol or assignment symbol. In STL it comes after the Jump (JU) instruction. An unconditional jump instruction causes a program jump to a label regardless of the RLO.
Network 1
M001
( JMP )
LAD Diagram
Network 2 : : Network n
( )
Jump Label
The label may be as many as four characters of which the first character must be a letter. Example: M001: A I 0.0
Network 1 JU M001
STL
Network 2 : : : : Network n M001: AN M50.0 AN I 44.1 = M99.7 13/8 November 21, 2013
SIMATIC S7
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Conditional Jump
The "JC" conditional jump is only executed if the RLO is "1". The "JCN" conditional jump is only executed if the RLO is "0". Note: STL provides additional jump operations
I 0.0
I 0.1
M002 (JMP)
LAD Diagram
( )
Network 1 A I 0.0 A I 0.1 JC M002 Network 2 : : : : Network n M002:
STL
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Answer of Exercise 1:
Answer of Exercise 3:
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Answer of Exercise 2:
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