BG3 Datapath Control

T chc my tnhHc k 2 2010-2011
Bi 3: Datapath v Control(c ch4: 4.1

4.5) H Vit Vit
ThS. GVC B mn K thut my tnh, Khoa in t Vin thng i hc Bch khoa Nng hoviet.viet@gmail.com
Hc k 2 2010-2011
T chc my tnh
Mc tiu Bi 3
Thit k phn cng cho mt cu lnh c th i vi mt
b x l MIPS single-cycle c tp lnh n gin
Hc k 2 2010-2011
T chc my tnh
Gian bp ca Von Neumann

Bt u ALU
Control Cc thanh ghi PC Chn mn Processo r

Program
Inpu t
Hc k 2 2010-2011
Dat a
Memor y
T chc my tnh
Outpu t
S vic bt u t u?
T mt thanh ghi: program counter (PC). PC cha a ch ca lnh k tip cn phi

u tin, PC cha a ch ca v tr nh
bt u chng trnh. thc hin.
Hc k 2 2010-2011
T chc my tnh
Chng trnh u?
Processo r Program counter (PC) Bt u M my ca chng trnh B nh
Hc k 2 2010-2011
T chc my tnh
Chng trnh c thc hin?

Bt u PC cha a ch bt u chng trnh Ly t lnh ti v tr nh c a ch PC v PC PC + 4 chun b cho lnh k tip Gii m lnh Thc hin lnh
Lu kt qu vo thanh ghi hoc b nh

Cha Xong ST OP
Hc k 2 2010-2011
Xong chng trnh T chc my tnh
Datapath v Control
Datapath: B nh, Cc thanh ghi, Cc b cng, ALU, v cc
bus thng tin. Mi bc (Ly lnh, gii m, thc hin, lu
kt qu) cn truyn d liu gia b nh, cc thanh ghi v

ALU.
Control: Datapath cho mi bc c duy tr bi cc tn

hiu iu khin . Cc tn hiu iu khin c to ra t n v control nhm ch hng truyn d liu trn bus thng tin
v ch nh chc nng cho ALU v b nh

Hc k 2 2010-2011 T chc my tnh
Datapath cho Ly lnh
Add 4 T lnh i ti cc thanh ghi v Control
PC
a ch
B nh lnh
Hc k 2 2010-2011
T chc my tnh
File thanh ghi: mt thnh phn ca Datapath

5 Read registers
Write register Write data 5 reg 1 reg 2 32 Registers (reg. file) 3 2 reg 2 data 3 2 reg 1 data
3 2
RegWrite n t Control
Hc k 2 2010-2011
T chc my tnh
ALU c th thc hin nhiu php ton Cc tn hiu chn php ton
Chn php ton ALU
000 AND 001 OR 010 Add 110 Subtract 111 Set on less than
n t Control 3 ALU zer o kt qu
overflow
zero = 1, khi mi bit ca kt qu bng 0
Hc k 2 2010-2011
T chc my tnh
Cc lnh kiu R
Cc lnh s hc v logic add, sub, slt V d: add $t0, $s1, $s2

oM my ca lnh 000000 10001 10010 01000 00000 100000 Opcode $s1 $s2 $t0 function oc 2 thanh ghi t File thanh ghi oGhi kt qu vo 1 thanh ghi oOpcode v function i ti Control to ra tn RegWrite v cc tn hiu chn php ton Hc khiu 2 2010-2011 T chc my tnh
Datapath cho lnh kiu R

000000 10001 10010 01000 00000 100000 opcode $s1 $s2 $t0 function (add) Read register numbers 100105 Write 5 01000 reg. number Write 3 data 2 100015 $s1 Cc tn hiu chn Php ton 3 2 3 2 3 ALU
$s2
32 Registers (reg. file)
zer o
overflow
result
$t 0
RegWrite
Hc k 2 2010-2011
T chc my tnh
Load v Store
Cc lnh kiu I lw $t0, 1200 ($t1)

100011 01001 01000 0000 0100 1011 0000
opcode $t1 $t0 1200
sw $t0, 1200 ($t1)

101011 01001 01000 0000 0100 1011 0000
opcode $t1 $t0 1200

Datapath cho lw
100011 01001 01000 0000 0100 1011 0000 opcode $t1 $t0 1200
Read 0100 register1 numbers 5
MemWrite
$t 1
3 2 AL U
Operation select from control (add) result
zero
Read data Addr. Data memory Write data
Write reg. 5 0100 number 0 Write data 3 2
overflow $t 0 3 2
RegWrite from control activated 1 6
0100 1011
Sign exten d
MemRead activated
mem. data to $t0

T chc my tnh
Hc k 2 2010-2011
Datapath cho sw
101011 01001 01000 0000 0100 1011 0000 opcode $t1 $t0 1200
Read 0100 register1 5
MemWrite activated
$t 1
$t 0 32 Registers (reg. file)
numbers 5 0100 0 Write reg. number Write data 3 2 5
3 2 AL U
Operation select from control 3 (add) zero result
Read data Addr. Data memory Write data
overflow
RegWrite from control
3 2
$t0 data to mem.
3 2
0100 1011
1 6
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Sign exten d
MemRead
T chc my tnh
Lnh r nhnh (kiu I)
beq $s1, $s2, 25 # nu $s1 = $s2, PC b

qua 25 lnh
16-bits
000100 10001 10010 0000 0000 0001 1001

opcode $s1 $s2 25
Lu : C th r nhnh trong phm vi 215 lnh t a ch hin
thi trong PC.

Datapath cho beq

16-bits 000100 10001 10010 0000 0000 0001 1001 opcode $s1 $s2 25
1000 Read 1 register numbers 5 1001 0 5 Write reg. number Write data 3 2 RegWrite from control 5 $s 1 Operation select from control (subtract) 3 3 2 zero AL result 3 U overflow 2
$s 2
To branch control logic

Branc h target
3 2
00 0000 0001 1 6 01
Sign exten d
PC+ From instruction 4 fetch datapath Shift left 2

3 2
3 2
Ad d
3 2
Hc k 2 2010-2011
T chc my tnh
Lnh J (kiu J)
j 2500 # nhy n lnh ti 10000

26-bits
000010 0000 0000 0000 0010 0111 0001 00
opcode 2,500
0000 0000 0000 0000 0010 0111 0001 0000bits 28-31 from PC+4
32-bit jump address
Datapath cho J
4
Add
Branc h addr.3 2 PC+ 4 Branc h
1 mux 0
4
3 2
Jum p 0 mux 1 2 8
3 2
3 2
Shift left 2 3 2
PC
Address
Instruction Memory
3 2
2 6
opcode (bits 26-31) to control
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T chc my tnh
Instruction word to control and registers
0-25
Shift
left 2
Jum p
0 mux 1 Add opcode CONTROL

26-31
Branc h
ALU
1 mux 0
MemtoReg
RegDs t
21-25
PC
Instr. mem.
Reg. File 16-20 1 mux 0 1 mux 0

11-15
ALU
zero
MemWrit e MemRead
Data 0 mux 1 mem.

ALU Cont.
0-15
0-5
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Sig n ext.
Shift left 2
T chc my tnh
Control
RegDst
Jump Branch Instruction Contro l Logic MemRead MemtoReg ALUOp MemWrite ALUSrc 2 RegWrite
bits 26-31 opcode
Instruction bits 0-5 funct.

Hc k 2 2010-2011
ALU Contro l
to ALU
T chc my tnh
Control Logic: Truth Table

Inputs: instr. opcode bits Instr type 31 30 29 28 27 26 0 1 0 0 0 0 0 0 0 1 0 1 Outputs: control signals
Re gD st Ju mp AL US rc Me mt oR eg Re gW rite Me m Re ad Me m Wri te Br an ch AL O Op 1 AL UO p2
R lw
1 0
0 0
0 1
0 1
1 1
0 1
0 0
0 0
1 0
0 0
sw
beq j
1
0 0
0
0 0
1
0 0
0
1 0
1
0 1
1
0 0
X
X X
0
0 1
1
0 X
X
X X
0
0 0
0
0 X
1
0 0
0
1 X
0
0 X
0
1 X
Hc k 2 2010-2011
T chc my tnh
Thi gian cho mt lnh?
Gi s control hot ng nhanh th thi Lnh s hc (kiu R)

c thanh ghi 1ns
Hot ng ca ALU 2ns Ghi thanh ghi 1ns
Hc k 2 2010-2011
gian dnh cho mt lnh ch yu l thi gian lm vic ca ALU, thi gian c/ghi b nh v thi gian c/ghi thanh ghi.
Ly lnh (c b nh) 2ns
Tng cng 6ns
T chc my tnh
Thi gian cho lw v sw (Kiu I)
Lnh s hc (kiu R) 6ns Load word (kiu I)

oLy lnh (c b nh) 2ns oc thanh ghi 1ns oHot ng ALU 2ns oLy d liu (c b nh ) 2ns oGhi thanh ghi 1ns oTng cng 8ns
T chc my tnh
Store word (khng ghi thanh ghi) 7ns

Hc k 2 2010-2011
Thi gian cho beq (Kiu I)
S hc (R) 6ns Load word (I) 8ns Store word (I) 7ns Branch on equal (I)
oLy lnh (c b nh) 2ns
oc thanh ghi 1ns

oHot ng ALU 2ns
Hc k 2 2010-2011
oTng cng 5nsT chc my tnh
Thi gian cho Jump (Kiu J)
S hc (R) 6ns Load word (I) 8ns Store word (I) 7ns Branch on equal (I) 5ns Jump (J):
oLy lnh (c b nh) 2ns oTng cng 2ns
Chu k ng h phi bng ?
Nu mi lnh phi c thc hin trong

mt chu k ng h th:
oChu k ng h t nht phi bng 8ns c th hon tt lnh lu nht l lnh lw.
oy gi l b x l Single-Cycle.
Phng php tng tc: B x l Multicycle

v Pipelining.
oCc lnh khc cng tn chng y thi gian.
Tm tt
c th thit k datapath v control cn

phi bit khun dng (kiu) ca cc cu lnh: R, I, J
Tt c cc lnh ca mt b x l SingleCycle u c thc hin trong mt chu k ng h (mc d thi gian cn thit c th b hn)

BG3 Datapath Control

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T chc my tnhHc k 2 2010-2011

Bi 3: Datapath v Control(c ch4: 4.1

Gian bp ca Von Neumann

Control Cc thanh ghi PC Chn mn Processo r

T mt thanh ghi: program counter (PC). PC cha a ch ca lnh k tip cn phi

Chng trnh c thc hin?

Lu kt qu vo thanh ghi hoc b nh

Xong chng trnh T chc my tnh

kt qu) cn truyn d liu gia b nh, cc thanh ghi v

Control: Datapath cho mi bc c duy tr bi cc tn

v ch nh chc nng cho ALU v b nh

Datapath cho Ly lnh

Add 4 T lnh i ti cc thanh ghi v Control

File thanh ghi: mt thnh phn ca Datapath

n t Control 3 ALU zer o kt qu

zero = 1, khi mi bit ca kt qu bng 0

Cc lnh s hc v logic add, sub, slt V d: add $t0, $s1, $s2

Datapath cho lnh kiu R

32 Registers (reg. file)

Cc lnh kiu I lw $t0, 1200 ($t1)

opcode $t1 $t0 1200

sw $t0, 1200 ($t1)

opcode $t1 $t0 1200

Operation select from control (add) result

Read data Addr. Data memory Write data

Write reg. 5 0100 number 0 Write data 3 2

RegWrite from control activated 1 6

mem. data to $t0

numbers 5 0100 0 Write reg. number Write data 3 2 5

Operation select from control 3 (add) zero result

Read data Addr. Data memory Write data

RegWrite from control

$t0 data to mem.

Lnh r nhnh (kiu I)

beq $s1, $s2, 25 # nu $s1 = $s2, PC b

000100 10001 10010 0000 0000 0001 1001

thi trong PC.

Datapath cho beq

32 Registers (reg. file)

To branch control logic

PC+ From instruction 4 fetch datapath Shift left 2

j 2500 # nhy n lnh ti 10000

000010 0000 0000 0000 0010 0111 0001 00

32-bit jump address

opcode (bits 26-31) to control

Instruction word to control and registers

0 mux 1 Add opcode CONTROL

Reg. File 16-20 1 mux 0 1 mux 0

Data 0 mux 1 mem.

bits 26-31 opcode

Instruction bits 0-5 funct.

Control Logic: Truth Table

Thi gian cho mt lnh?

Gi s control hot ng nhanh th thi Lnh s hc (kiu R)

Tng cng 6ns

Thi gian cho lw v sw (Kiu I)

Lnh s hc (kiu R) 6ns Load word (kiu I)

Store word (khng ghi thanh ghi) 7ns

Thi gian cho beq (Kiu I)

oc thanh ghi 1ns

oTng cng 5nsT chc my tnh

Thi gian cho Jump (Kiu J)

Chu k ng h phi bng ?

Nu mi lnh phi c thc hin trong