Akash Bansal -2013H123033G Viraj Barwatkar-2013H140060G Vineeth Kartha -2013H140062G

Introduction Net modelling of nodes -bounded Unidirectional Bi-partitioning Multi-way Precedence Constrained Partitioning Example References

Dynamically Reconfigurable FPGA, it needs to be partitioned such that each sub-circuit can be executed at a different time. To ensure the correctness of the execution, minimize the number of interconnection among the partitions as well as both the area and pin constraints. Nodes have precedence constraints among themselves. Network flow based approach is used for multiway precedence constrained partitioning problem.

Circuit represented by directed hypergraph G(V,N) Where, V: set of nodes N: set of nets Two types of nodes:
Combinational nodes (C-nodes)

Flip-flop nodes (FF-nodes)

Each c-node must be scheduled in a stage no later than all its output nodes. Each FF-node must be scheduled in a stage no earlier than all its input c-nodes. This rule guarantees that flip-flop input values are calculated before they are stored. Each FF-node must be scheduled in a stage no earlier than all its output nodes. This rule guarantees that all the nodes that use the value of the flip-flop use the same value: the value of the flip-flop from the previous user cycle

Partitioning a circuit of total weight W into two disjoint subsets X and X. w(X) deviation can be (1-) to (1+) For k-way precedence constrained partitioning, = w(V)/k; minimizing maximum number of nodes in any stage to allow the design fit on a smaller physical FPGA

Each cut between the two adjacent stages i and i+ 1 must be uni-directional Repeatedly apply the bipartitioning algorithm FBP-u k-1 times to find a uni-directional cut. depth - the number of nodes on the longest critical path in the netlist The number of levels in one stage is
depth L k

To minimize the maximum number of nodes in any stage in order to allow the design to fit into a smaller physical FPGA, make each stage have weight as close to the average, w(V) /k.

Critical path length i.e. depth=9 L=depth/k Here k=3 So L=3; =15/3 =5;

Huiqun Liu and D. F. Wong, Network Flow Based Circuit Partitioning for Time-multiplexed FPGAs" Honghua Yang and D.F.Wong, Efficient Network Flow Based Min-Cut Balanced Partitioning", Proc. International Conference on Computer Aided Design, 1994.