Digital Logic Design

Lecture # 10 University of Tehran

Outline

More Examples on Realizing Functions Using Multiplexer Other Applications for Multiplexer Comparator Full Adder

More Examples on Realizing Functions Using Multiplexer

Last session we saw how to realize a switching function using a KM by relating the MUXs inputs to the columns of the KM. We will now do the same only this time using the KMs rows. Consider for instance the following KM:
ab cd 00 0 1 1 0 3 10 2 1 6 7 1 14 5 1 15 1 10

c d

00 1 4

01 1 12 1 13

11 0 8 0 9 0 11

10 0

01

11

a b a b a b

0 1 2 3

1 0 z

More Examples on Realizing Functions Using Multiplexer (continued)

In the last design a lot of glue logic has been used alongside the MUX package. We can resolve this problem if we use an 8-to-1 MUX instead:
abc

1 d 1 1 d d 0 d

2 1 0 0 1 2 3 z 4 5 6 7

Other Applications for Multiplexer

Another application for multiplexers is the transition of data between multiple sources and destinations
S1 S2 S3 S4

?
D1

D2

D3

D4

In the above figure, suppose each source has a 4 bit output.

Other Applications for Multiplexer (continued)

One way to solve this problem could be to simply use one quad 4-to-1 multiplexer behind each Di with which each source can easily send data to any required destination at one time. One problem with this approach is that it leaves us with a lot of wiring, and also we will not have much ability in increasing the number of sources as all of our multiplexers will have to be changed.
S1 S2 S3 S4 4 4 4 4 01 1 2 3
0

4 4 4 4 4

D1 D2 D3 D4

Other Applications for Multiplexer (continued)

Note: The structure used in between the MUX and the destinations is called a bus.

4 4 4 4 4

Other Applications for Multiplexer (continued)

A better solution to the problem is to use three state buffers on the output of each source with a common control line for all buffers relating to a particular source. Bye doing this only one source will have the ability to drive a particular destination at any instance of time. To select which source will have this ability is done by the use of a decoder (that can be initially selected larger to support a larger number of source that may be used in the future). The figures shown in the next slide, shows this design.

Other Applications for Multiplexer (continued)

S1 4 select1
ENB

S2 4 select2
ENB

S3 4 select3
ENB

S4 4 select4
ENB

4 4 D4

4 4 D3

4 4 D2

4 4 D1

Other Applications for Multiplexer (continued)

Again another solution for the problem that is very difficult to implement on a board is:
S1 4 select1 select2 S2 4 select3 S3 4 select4 S4 4

4 4 D4 D3 4 D2 4 D1 4

Comparator

To test the equality of two numbers the following circuit can be used (two 4 bit numbers):
a 0 0 1 1 b z 0 1 1 0 0 0 1 1
a0 b0 a1 b1 a2 b2 a3 b3

XNOR

Comparator (continued)

The above circuit is very straightforward to understand considering what an XNOR gate does. The following circuit tests the inequality a>b, by first testing to see whether a3 is 1 and b3 is 0 and doing the same test for lower bits if these bits are equal.
a0 b0

a1 b1

a2 b2

a3 b3

Comparator (continued)

The 7485 is a standard comparator package with the following attributes: if (A>B) lt=0, eq=0, gt=1 if (A<B) lt=1, eq=0, gt=0 4 A if (A=B) lt=l, eq=e, gt=g B
4 l e g lt eq gt

Quote: The three l, e and g inputs are used when cascading.

Comparator (continued)

Let us now cascade four of the 7485 to construct a 16 bit comparator.

a[ 15:0 ] b[ 15:0 ]
[15:12] [15:12] [11:8] [11:8] [7:4] [7:4] [3:0] [3:0]

4 A 4 B l e g

4 lt eq gt 4

A B l e g

4 lt eq gt 4

A B l e g

4 lt eq gt 4 0 1 0

A B l e g

lt eq gt

gt eq lt Final results of comparison

Comparator (continued)

This comparator will first compare the 4 most significant bits of the two inputs, unless they are equal the result can be found in this first stage as a is less than b if its 4 MSB are smaller and is greater if the 4 MSB are larger. If these 4 MSB of the two numbers turn out to be equal, the comparator will recursively do the same comparison on less significant bits four by four.

Comparator (continued)

The comparators we have seen so far have been magnitude comparators, that is they only work correctly when their inputs are unsigned numbers. To be able to use the same comparators for 2s complement numbers, some glue logic needs to be used which is:
a3 b3 gt 0 1 1 0 1 3 00 0 2 1 7 01 1 6 1 5 sgt 11 0 4 0 10 0

a3 b3 lt 0 1 1 0

00 0 2 1 3

01 0 6 0 7

11 0 4 1 5

10 1

1 slt

sgt a 3.b3 a 3.gt b3.gt

slt a 3.b3 lt.a 3 lt.b3

Comparator (continued)

Lets design a maximum finder using a comparator and a MUX:

a b 4 4 0 1 0 l e g 4 4 A B lt eq gt

0 1

Max(a,b)

Full Adder

Last session we saw how to implement a full adder using a MUX, continuing our discussion of arithmetic units we will now see a full adder realization with discrete gates.
a b

cin

F . A.
sum

cout

abci 000 001 010 011 100 101 110 111

cos 00 01 01 10 01 10 10 11

Full Adder (continued)

ab ci 0 1 1 0 1 3 00 0 2 0 7 01 1 6 1 5 s 11 0 4 0 10 1

ab ci 0 1 1 0

00 0 2 0 3

01 0 6 1 7

11 1 4 1 5

10 0

1 co

Full Adder (continued)

The logic diagram is:

a b ci s

co

Full Adder (continued)

The figure shown in the last slide, shows how to realize a 1 bit full adder, for a 4 bit full adder rippling the carry through each stage we may have:
b3 a3 b2 a2 b1 a1 b0 a0

F.A.

F.A.

F.A.

F.A.

Cout

S3

S2

S1

S0

The above adder is called Pseudo Parallel or Ripple Carry adder.

Full Adder (continued)

The last design can also be used to subtract two 4 bit numbers, considering how subtraction of 2s complement numbers is done in practice. All we have to do is complementing the bits of b and setting the first stages carry to 1.