ECE 428 Programmable ASIC Design

FPGA Implementation of Sequential Logic

Haibo Wang ECE Department Southern Illinois University Carbondale, IL 62901
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Sequential Circuit Model

Combinational Circuit: the circuit outputs are a logic combination of the current inputs signals. Sequential Circuit: the circuit outputs depend on not only the current values of inputs but also previous input values.
Circuit outputs

Circuit inputs

Combinational Circuits

Storage elements

clock

A model for sequential circuits

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Storage Elements in Xilinx CLB

Each CLB contains two edge-triggered D flip-flops. They can be configured as positive-edge-triggered or negative-edge-triggered. Each D flip-flop has clock enable signal E, which is active high. Each D flip-flop can be set or reset by SR signal. A global reset or reset signal is also available for set or reset all D flip-flops once the device is powered up.
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Circuit Techniques to Avoid Clock Glitches

If possible, try to avoid connecting the output of combinational logic to D flip-flop clock input.

Enable Clock

D Q E

Clock Enable Output

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FPGA Implementation of Finite State Machines

Example of Finite State Machine
xx Current States S0 Inputs: xy 0x S3 S3 S3 10 11 a 0 1 0 Outputs b c 0 0 0 1 0 0 d 1 1 0 e 1

S3
0x

S1 S2 S1 S2 S3 S3

S1

S2 S2 S2

0 1 0 1

1
0 0

S0
10 11 xx 10

0x

S2 S3

S1

S2

11

State Table Note: this is a Moore-type machine. The design procedure for mealy-type machine is similar.
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State transition diagram

State Encoding
Binary encoding: minimum number of D flip-flops
Q1 Q0

S0 : S1 : S2 : S3 :

0 0 1 1

0 1 0 1

It needs two D flip-flps

One-hot encoding: one D flip-flop for each state

Q3 Q2 Q1 Q0

S0 : S1 : S2 : S3 :

0 0 0 1

0 0 1 0

0 1 0 0

1 0 0 0

It needs four D flip-flps

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Implementation Using Binary Encoding

Excitation table
Inputs x 0 0 0 0 1 1 1 1 1 1 1 1 y x x x x 0 0 0 0 1 1 1 1
Current States

Next States D1 1 1 1 1 0 1 0 1 1 1 1 1 D0 1 0 1 1 1 0 1 1 0 0 0 1

Q1 0 0 1 1 0 0 1 1 0 0 1 1

Q0 0 1 0 1 0 1 0 1 0 1 0 1

Outputs a b c 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0

d 1 1 1 0 1 1 1 0 1 1 1 0

e 1 1 0 0 1 1 0 0 1 1 0 0
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Implementation Using Binary Encoding

Combinational functions needed to be implemented
D1 = x+ y + Q0
D0 = Q1Q0 + yQ0 + xQ0 a = Q1Q0

(F1)
(F2) (F3)

b = Q1Q0
c = Q1Q0 d = Q0 + Q1 e = Q1

(F4)
(F5) (F6) (F7)

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Implementation Using Binary Encoding

FPGA implementation
Reset

CLB
Q1 1 y x LUT F1 D Q F3, F4 e Q0 y x LUT F2 F5, F6 D Q CLB c CLB

a b

Clk

It needs three CLBs

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Implementation Using One-Hot Encoding

The next state and output functions have a simple, systematic form Next state function

Di Q j ( I j ,1 I j ,2 I j ,n )
Di is the input of the D flip-flop that represents state Si Qj is the output of the D flip-flop that represent state Sj Ij,1, Ij,2, .. and Ij,n denote all input combinations that cause a state transition from Sj to Si

Output function

z k Qk ,1 Qk , 2 Qk ,m
zi is an FSM output Qk,1, Qk,2, .. and Qk,m denote all states (D flip-flip outputs) that cause output zk to be 1
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Implementation Using One-Hot Encoding

Combinational functions needed to be implemented
D0 = 0 D1 = Q0xy + Q2xy D2 = Q0xy + Q1 + Q2x y D3 = Q0x + Q2 x + Q3 a = Q2 b = Q1 c = Q0 d = Q0+Q1+Q2 e = Q0+Q1 (F5) (F6)
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(F1) (F2) (F3) (F4)

Implementation Using One-Hot Encoding

FPGA implementation
Reset

Q0
CLB
0 D Q

c b

Q0 x y Q2

LUT F2

D Q

Q1

d
F5, F6 Q2
D Q

e
CLB

Q0 x y Q1 Q2 Q0 x Q2 Q3

LUT

F3

LUT

Q3
D Q

a
It needs three CLBs

LUT F4

CLB

Clock

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Comparison of Binary Encoding and One-Hot Encoding

Binary encoding
Fewer flip-flops It normally needs complicated combinational logic to determine next state and output signals. The complicated logic may decrease circuit performance. May have glitches

One-hot encoding
More flip-flops It normally has simple combinational logic for next state transitions and output signals. It is suitable for high performance system design. It is unlikely to have glitches.

FPGAs have plenty of flip-flops. Thus, it is preferred to use one-hot encoding in FPGA FSM implementations.
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Possible Glitches in Binary-Encoded FSMs

Desired transition 1010 01 10

11

Actual transition 011110

O

Glitch

Q1

Q0

CLK

delay
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Possible Lock-up States in Binary-Encoded FSMs

When unused states exist in a binary-encoded FSM, make sure there are no lock-up states.
Example: for a three state FSM, it needs two D flip-flops to implement binary encoding scheme. Assume 01, 10, 11 are the three used states. 00 is the unused state, make sure that FSM will not be trapped in 00 state.

01

10

Lock-up state
00

01

10

11
Used states

11 Used states

00

Not a lock-up state

Unused state

Unused state

To avoid lock-up states, make sure the FSM will eventually move from any
unused state to an used state. Another method is to use reset (or set) signals to reset (or set) FSM to an used state (initial state) after power-up.
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Implement Complex FSM using embedded Memories

Latest FPGAs often contain embedded memories. Complicated FSMs can be implemented by using the embedded memories.
memory
FSM inputs Previous inputs

DFF
Previous states clock

Current state FSM outputs decoder FSM outputs

It is similar to the microprogram mechanism used in CISC computers.

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