What Makes a Design Difficult to Route

Charles J. Alpert, Zhuo Li, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, Gustavo Tellez Presented by Zhicheng Wei

Lienig

VLSI Physical Design: From Graph Partitioning to Timing Closure

Chapter 6: Detailed Routing

KLMH

What Makes a Design Difficult to Route

KLMH

INTRODUCTION AND BACKGROUNDS COMMON CONGESTION METRICS GLOBAL ROUTING CONSTRAINTS DETAILED ROUTING CONSTRAINTS PLACEMENT TECHNIQUES LOGIC SYNTHESIS TECHNIQUES REPEATER INSERTION TECHNIQUES CONCLUSION

Lienig

VLSI Physical Design: From Graph Partitioning to Timing Closure

Chapter 6: Detailed Routing

What Makes a Design Difficult to Route

KLMH

INTRODUCTION Modern technology requires complex wire spacing rules and constraints High performance routing requires multiple wire width (even same layer) Local problems including via spacing rules, switchbox inefficiency, intra-gcell routing

All of these problems make routing hard to model and lead to huge congestion issues!

Lienig

VLSI Physical Design: From Graph Partitioning to Timing Closure

Chapter 6: Detailed Routing

What Makes a Design Difficult to Route

KLMH

BACKGROUNDS Routing problems should be considered in 3D instead of 2D Meet congestion constraints during global routing Try to satisfy capacity in detailed routing with a given global routing solution Over-the-cell routing breaks traditional channel/switchbox model

Lienig

VLSI Physical Design: From Graph Partitioning to Timing Closure

Chapter 6: Detailed Routing

What Makes a Design Difficult to Route

KLMH

COMMON CONGESTION METRICS Total Overflow Average worst X% average worst 20% routing edges below 80% is routable Total routed wirelength (RWL) significantly above Steiner tree may indicate routing difficulties Number of scenic nets wirlelength/minimum Steiner tree length ratio > 1.3 is generally considered scenic Number of nets over X% nets passing through gcells whose congestion is over X% Number of violations Routing runtimes

Lienig

VLSI Physical Design: From Graph Partitioning to Timing Closure

Chapter 6: Detailed Routing

What Makes a Design Difficult to Route

KLMH

COMMON CONGESTION METRICS Total Overflow

Lienig

VLSI Physical Design: From Graph Partitioning to Timing Closure

Chapter 6: Detailed Routing

What Makes a Design Difficult to Route

KLMH

GLOBAL ROUTING CONSTRAINTS Choice of gcell size gcell size too small large global routing space and takes more time to route gcell size too large not able to expose congestion problems and shift burden to detail routing Handling scenic nets go very scenic = bad timing performance impose scenic constrains on the router

Lienig

VLSI Physical Design: From Graph Partitioning to Timing Closure

Chapter 6: Detailed Routing

What Makes a Design Difficult to Route

KLMH

DETAILED ROUTING CONSTRAINTS Prediction failure in global routing hot sports predicted by global routing may not be open and shorts in detailed routing

Lienig

VLSI Physical Design: From Graph Partitioning to Timing Closure

Chapter 6: Detailed Routing

What Makes a Design Difficult to Route

KLMH

DETAILED ROUTING CONSTRAINTS Pin access problem certain configurations make accessing pin from higher metal layer impossible Via modeling challenge Vias do not scale as well as device at each technology node Vias serve as routing blockages which impact local congestion Via modeling becomes non-trivial, esp with different metal pitches

Lienig

VLSI Physical Design: From Graph Partitioning to Timing Closure

Chapter 6: Detailed Routing

What Makes a Design Difficult to Route

KLMH

PLACEMENT TECHNIQUES Congestion caused by time-driven placement

Lienig

VLSI Physical Design: From Graph Partitioning to Timing Closure

Chapter 6: Detailed Routing

10

What Makes a Design Difficult to Route

KLMH

PLACEMENT TECHNIQUES Modern placement focus on minimization of HPWL Uniform placement does not always work! Uniform placement does not mean uniform wire spreading! Consider congestion-driven placement

Lienig

VLSI Physical Design: From Graph Partitioning to Timing Closure

Chapter 6: Detailed Routing

11

What Makes a Design Difficult to Route

KLMH

PLACEMENT TECHNIQUES Congestion Reduction by Iterated Spreading Placement (CRISP) Selectively spreading the placement in regions with high global congestion

Lienig

VLSI Physical Design: From Graph Partitioning to Timing Closure

Chapter 6: Detailed Routing

12

What Makes a Design Difficult to Route

KLMH

LOGIC SYNTHESIS TECHNIQUES Logic synthesis generally ignores placement information Create structures good for timing closure but bad for routing Logic synthesis transforms to alleviate local congestions identify logic fan-in tree which is physically wirelength inefficient rebuild logic tree and place new synthesized gates wirelength is minimized and congestion alleviated

Lienig

VLSI Physical Design: From Graph Partitioning to Timing Closure

Chapter 6: Detailed Routing

13

What Makes a Design Difficult to Route

KLMH

REPEATER INSERTION TECHNIQUES Repeaters are inserted to meet timing constraints Divide long wires into small segments Layer assignment Obtain enormous speed advantage using thick metal for most critical paths Routing congestions caused Corona effect (congestion around corner of blockages) Aggressive layer promotion (fewer resources at higher metal layer)

Lienig

VLSI Physical Design: From Graph Partitioning to Timing Closure

Chapter 6: Detailed Routing

14

What Makes a Design Difficult to Route

KLMH

Aggressive Layer Promotion

Lienig

VLSI Physical Design: From Graph Partitioning to Timing Closure

Chapter 6: Detailed Routing

15

What Makes a Design Difficult to Route

KLMH

Corona Effect

Lienig

VLSI Physical Design: From Graph Partitioning to Timing Closure

Chapter 6: Detailed Routing

16

What Makes a Design Difficult to Route

KLMH

CONCLUSION Physical synthesis issues in placement, global/detail routing, logic synthesis Advanced technologies require more complicated modeling plan Capture more detailed routing effects in global routing stage Estimation techniques need to be fast to optimize routing fast

Lienig

VLSI Physical Design: From Graph Partitioning to Timing Closure

Chapter 6: Detailed Routing

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