EECL 309B Digital System Design using VHDL

Spring 2014 Semester

Books followed
Volnei A. Pedroni, Circuit Design with VHDL. Douglas L. Perry, VHDL Programming by Example. J Bhasker, A VHDL Primer.

Design Abstraction
How do we describe a system?

Design Abstraction
Example: Design a system which will complement input A

F(x)

Y=A

A and Y are single bit values We can describe this design using a logical Truth Table
A Y

0
1

1
0

Levels of Design Abstraction

Our goal in ECE is physical or hardware implementations of the design.
0 1 Vcc1 a1 b1 5

Design Specs

Design Process

a2

a3

Hardware
GND 0

b2

b3

a4

b4

In ECE, we design at several levels of abstraction

Levels of Design Abstraction

System: Assembly Language Behavioral: VHDL Logical: Gates Electronic Circuit: Transistors Integrated Circuit: IC Layout Fabrication: IC Processing

Levels of Design Abstraction

Example: Design a system which will complement input A

System Level:

ASM Code
NEG A

Y=A

8085 Assembly Language

Levels of Design Abstraction

Example: Design a system which will complement input A

Behavioral Level:

Not A
VHDL

Y=A

Y <= not A;

Levels of Design Abstraction

Example: Design a system which will complement input A Gate Level:

Y=A

Inverter or NOT gate

Levels of Design Abstraction

Example: Design a system which will complement input A Circuit Level: PFET
Vdd

Y=A

NFET

CMOS Technology

Levels of Design Abstraction

Example: Design a system which will complement input A Digital IC Design:

Y=A
VDD GND

CMOS Technology

Levels of Design Abstraction

Fabrication Level:

P+

P+

N+

N+

NWELL

PSUB

Gajskis Y-chart
Each axis represents type of description
Behavioral

Structural

Behavior Sequential programs Register transfers Logic equations/FSM Transfer functions Cell Layout Modules Chips Boards Physical

Defines outputs as function of Processors, inputs memories Registers, FUs, Algorithms but no implementation MUXs Implements behavior by connecting components with known behavior

Structural

Gates, flip-flops Transistor s

Physical

Gives size/locations of components and wires on chip/board

Design process is illustrated by travel route

VHDL Introduction
V- VHSIC
Very High Speed Integrated Circuit

H- Hardware D- Description L- Language

VHDL for Simulation & Synthesis

Test Vector Generator

Executable Specificatio n

Results , Errors

Test Vectors

A Series of Refined Models

Final Chip
Model

Reasons for using VHDL

Shorter development times for electronic design Simpler maintenance Traditional way: schematic design

Origin of the VHDL

VHDL originated in the early 1980s
The American Department of Defense initiated the development of VHDL in the early 1980s
because the US military needed a standardized method of describing electronic systems

VHDL was standardized in 1987 by the IEEE It is now accepted as one of the most important standard languages for
specifying verifying designing of electronics

Standardization 1
IEEE standard specification language (IEEE 1076-1993) for describing digital hardware used by industry worldwide VHDL enables hardware modeling from the gate level to the system level All the major tool manufacturers now support the VHDL standard VHDL is now a standardized language, with the advantage that it is easy to move VHDL code between different commercial platforms (tools) => VHDL code is interchangeable among the different tools

Standardization 2
VHDL is an acronym of VHSIC Hardware Description Language VHSIC is an acronym of Very High Speed Integrated Circuits All the major tool manufacturers now support the VHDL standard VHDL is now a standardized language, with the advantage that it it easy to move VHDL code between different commercial platforms (tools) => VHDL code is interchangeable among the different tools

Standardization 3
It was the American Department of Defense which initiated the development of VHDL in the early 1980s because the US military needed a standardized method of describing electronic systems VHDL was standardized in 1987 by the IEEE
ANSI Standard in 1988 Added Support for RTL Design Revised version in 1993
IEEE Std-1076-1993 IEEE Std-1076-1987

VITAL: VHDL Initiative Towards ASIC Library

Standardization 4
1995:
numeric_std/bit: IEEE-1076.3 VITAL: IEEE-1076.4

1999: IEEE-1076.1 (VHDL-AMS ) 2000:

Added mixed-signal support to VHDL in 2001 ->

VHDL-AMS

IEEE-1076-2000 IEEE-1076.1-2000 (VITAL-2000, SDF 4.0)

2002: IEEE-1076-2002

IEEE Std-1076.1-2001

Tools
Good VHDL tools, and VHDL simulators in particular, have also been developed for PCs Prices have fallen dramatically, enabling smaller companies to use VHDL, too There are also PC synthesis tools, primarily for FPGAs and EPLDs

Usage
High-tech companies

Universities VHDL groups to support new users

Texas Instruments, Intel use VHDL most European companies use VHDL

IEEE
IEEE is the Institute of Electrical and Electronics Engineers The reference manual is called IEEE VHDL Language Reference Manual Draft Standard version 1076/B It was ratified in December 1987 as IEEE 10761987 Important:

the VHDL is standardized for system specification but not for design

Technology independence
The design of VHDL components can be technology-independent or more-or-less technology independent for a technical family The components can be stored in a library for reuse in several different designs VHDL models of commercial IC standard components can now be bought, which is a great advantage when it comes to verifying entire circuit boards

Analog world
VHDL has not yet been standardized for analog electronics Standardization is in progress on VHDL with an analog extension (AHDL) to allow analog systems to be described as well This new standard will be based wholly on the VHDL standard and will have a number of additions for describing analog functions

VHDL-Related Newsgroups
comp.arch.fpga comp.lang.vhdl comp.cad.synthesis

Other HDL languages

There are several other language extensions built to either aid in RTL construction or assist in modeling:
Verilog

ParaCore - http://www.dilloneng.com/paracore.shtml RubyHDL http://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/index.shtml MyHDL - http://jandecaluwe.com/Tools/MyHDL/Overview.shtml JHDL - http://www.jhdl.org/ Lava - http://www.xilinx.com/labs/lava/ HDLmaker - http://www.polybus.com/hdlmaker/users_guide/ SystemC AHDL http://www.altera.com
It is good for Altera-made chips only, which limits its usefulness But it

is easy to pick up and use successfully

The main purpose of a language -- programming, hdl, or

Fundamental sections of a basic VHDL code.

Example code - VHDL

Full-adder Schematic A VHDL code for the full adder

Simulation results from the VHDL design

VHDL Constructs
Entity definition Architecture definition Configuration Process Subprogram Package A VHDL design can be broken into multiple files. Each file contains entity and architecture definitions, or packages.

Overall structure of a VHDL file

Entity

Library declaration

Entity declaration

Architecture body

32

What are they?

A VHDL file Library declaration, e.g. IEEE library

Entity declaration

Entity
Architecture body
Architecture Body: defines the processing

VHDL 1. ver.3a

33

LIBRARY
A LIBRARY is a collection of commonly used pieces of code. Placing such pieces inside a library allows them to be reused or shared by other designs. The typical structure of a library is shown aside.

Library Declarations
To declare a LIBRARY (that is, to make it visible to the design) two lines of code are needed, one containing the name of the library,

and the other a use clause. The syntax is as follows LIBRARY library_name ; USE library_name.package_name.package_parts ;

Contd..

At least three packages, from three different libraries, are usually needed in a design : ieee.std_logic_1164(from the ieee library), standard (from the std library) , and work (work library)

Library Declarations
LIBRARY ieee; -- A semi-colon (;) indicates the end of a statement or a declaration USE ieee.std_logic_1164.all ; LIBRARY std ; -- a double dash (--) indicates a comment. USE std . Standard . all ; LIBRARY work ; USE work. all;

Contd..
The std_logic_1164 package of the ieee library specifies a multi-level logic system; std is a resource library (data types, text i/o, etc.) for the VHDL design environment; and the work library is where we save our design (the .vhd file, plus all files created by the compiler, simulator, etc.).

STD_LOGIC type
Value Meaning

U
X

Uninitialized
Forcing (Strong driven) Unknown

0 1 Z
W L H -

Forcing (Strong driven) 0 Forcing (Strong driven) 1 High Impedance

Weak (Weakly driven) Unknown Weak (Weakly driven) 0. Models a pull down.

Weak (Weakly driven) 1. Models a pull up.

Don't Care

ENTITY
Entity describes the design interface. The interconnections of the design unit with the external world are enumerated. The properties of these interconnections are defined.
entity declaration: entity <entity_name> is port ( <port_name> : <signal mode> <type>; . ); end <entity_name>;

Signals in Entity
There are four modes for the ports in VHDL in, out, inout, buffer These modes describe the different kinds of interconnections that the port can have with the external circuitry. Sample program: ENTITY andgate is
port ( c : out bit; a : in bit; b : in bit );

end andgate;

Contd..
The mode of the signal can be IN, OUT, INOUT, or BUFFER . IN and OUT are truly unidirectional pins, while INOUT is bidirectional. BUFFER, on the other hand, is employed when the output signal must be used (read) internally. The name of the entity can be basically any name, except VHDL reserved words

ARCHITECTURE
Architecture defines the functionality of the entity. It forms the body of the VHDL code. An architecture belongs to a specific entity. Various constructs are used in the description of the architecture. architecture declaration:
architecture <architecture_name> of <entity_name> is <declarations> begin <vhdl statements> end <architecture_name> ;

Contd An architecture has two parts : a declarative part (optional), where signals and constants (among others) are declared, and the code part (from BEGIN down).
architecture declaration: architecture <architecture_name> of <entity_name> is <declarations> begin <vhdl statements> end <architecture_name> ;

EXAMPLE OF A VHDL ARCHITECTURE

ENTITY andgate is port (c : out bit; a : in bit; b : in bit ); end andgate; ARCHITECTURE arc_andgate of andgate is begin c <= a and b; end arc_andgate;

Architecture Types
The digital system can be represented in different levels of abstractions such as a behavioral model or a structural model or a data flow. These levels of abstraction help the designer to develop any complex digital system efficiently.

1. Data Flow 2. Behavioral 3. Structural

Data Flow Modelling

A Dataflow model specifies the functionality of the entity without explicitly specifying its structure. This functionality shows the flow of information through the entity, which is expressed primarily using concurrent signal assignment statements and block statements. The primary mechanism for modeling the dataflow behavior of an entity is using the concurrent signal assignment statement. mostly used for design of combinational logics

Behavioral
Behavioral level describes the system, the way it behaves and describes the relationship between the input and output signals. The description can be a Register Transfer Level (RTL) or Algorithmic (set of instruction) or simple Boolean equations. Algorithmic level is mostly used for design of sequential logics.

Structural Modelling
The Structural level describes the digital system as gates or as component blocks interconnected to perform the desired operations. Structural level is primarily the graphical representation of the digital system and so it is closer to the actual physical representation of the system.

Complete AND GATE Example

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; Entity and_example is port(a,b: in std_logic; ya,yb,yc: out std_logic); End entity and_example; Architecture test of and_example is begin -- dataflow model (ya) ya <= a and b; -- structural model (yb) and2:a_7408 port map(a,b,yb); -- behavioral model (yc) process(a,b) begin yc <= 0; if((a=1) and (b = 1)) then yc <= 1; else yc <= 0;

end if;
end process; End architecture test;

AND GATE Example (cont)

When synthesized, we obtain the following logic circuit
A B

Synthesis tool creates three AND gates.

Ya

Yb

Block Diagram
Yc

An example of a comparator

Entity declaration

Architecture body

1 entity eqcomp4 is 2 port (a, b: in std_logic_vector(3 downto 0 ); 3 equals: out std_logic); Entity declaration: defines IO 4 end eqcomp4; 5 6 architecture dataflow1 of eqcomp4 is 7 begin 8 equals <= '1' when (a = b) else '0; Architecture 9-- comment equals is active high Body: defines 10 end dataflow1; the processing

How to read it?

Entity enclosed by the entity name eqcomp4 (entered by the user) Port defines the I/O pins.

Entity declaration

Architecture body

1 entity eqcomp4 is A bus, use downto to define it. E.g. in std_logic_vector( 3 downto 0); 2 port (a, b: in std_logic_vector( 3 downto 0 ); 3 equals: out std_logic); 4 end eqcomp4; 5 6 architecture dataflow1 of eqcomp4 is 7 begin 8 equals <= '1' when (a = b) else '0; 9-- comment equals is active high 10 end dataflow1;

Exercise
In the eqcomp4 VHDL code: How many Input / Output pins? Answer: _______ What are their names and their types? Answer: ___________ _______________ ____ What is the difference between std_logic and std_logic_vector? Answer: __________ _______________ ___
1 entity eqcomp4 is 2 port (a, b: in std_logic_vector(3 downto 0 ); 3 equals: out std_logic); 4 end eqcomp4; 5 6 architecture dataflow1 of eqcomp4 is 7 begin 8 equals <= '1' when (a = b) else '0; 9-- comment equals is active high 10 end dataflow1;