LOW-POWER LDPC DECODER IMPLEMENTATION USING LAYER DECODING

AJITH.C 212111419001 M.E VLSI Design

Guide BY Mr.P Kabilamani,Lecturer,ECE

Abstract

Method for creating LDPC codes which are specifically designed to be hardware friendly. Layer decoding is the one of the efficient approach to decode the LDPC code with good error rate performance. Proposed approach will efficiently decrease the power.

INTRODUCTION

LDPC Code is a Linear Error Correcting Code. LDPC codes are finding increasing use
1. reliable and highly efficient information transfer over bandwidth 2. return channelconstrained links in the presence of data-corrupting noise.

Error correcting code in the new DVB-S2

Cont

Representations for LDPC Codes Matrix and Graphical Representations

Existing Method

Layered Decoding

Cont

Most Practical LDPC Codes are structured to support layered decoders in hardware. This concept is usually generalized by dividing the H-Matrix into Layers. Only one CN can access a given VN memory at a specific time. In a layered decoder,one CN processor can be designed to serially process the different rows of the H-Matrix.

Proposed Method

Vectored Layer Decoding

Cont

Vector Decoder Architecture overcomes the limitation of the layered decoder by packing multiple messages in the same memory unit. Throughput of a vector decoder can be times that of a scalar decoder.

Phase I

LDPC Encoding

Phase II

LDPC Decoding using Layer Decoding. Vectored Layer Decoding.

LDPC Encoding

Generator Matrix from Parity Check Matrix. Encoding Technique.

Generator Matrix from Parity Check Matrix

Parity Check Matrix(H)

H(qxn)=[Pqxk : Iq ]. Generator Matrix(G)

G(kxn) =[Ik:Pkxq].

Encoding Technique

Encoding by Matrix Multiplication Systematic codeword Generation codeword,X=axGT a=(a ,a ,a ),k information bits to be encoded. GT=Generator Matrix Transpose
1 2 k

Software Used

Simulation : Xilinx ISE 9.1i

Simulation For H Matrix To G Matrix Generation

Cont..

Simulation For LDPC Encoding

References

R. Gallager, Low-density parity-check codes, IEEE Trans. Inf. Theory, vol. IT-8, no. 1, pp. 2128, Jan. 1962. Z. Li, L. Chen, L. Zeng, S. Lin, and W. Fong, Efficient encoding of quasi-cyclic low-density parity-check codes, IEEE Trans. Commun.,vol. 53, no. 11, p. 1973, Nov. 2005. E. Yeo, P. Pakzad, B. Nikolic, and V. Anantharam, High throughput low-density parity-check decoder architectures, in Proc. IEEE Global Telecommun. Conf., 2001, vol. 5, pp. 30193024.

THANK YOU