Unit V CMOS Testing

V.Vaithianathan, M.Tech, (Ph.D) Assistant Professor/ECE SSN College of Engineering

Discussion
Lecture 1 Need for Testing Lecture 2 Manufacturing Test Principles Lecture 3 Design Strategies for Test Lecture 4 Chip Level Test Techniques Lecture 5 System Level Test Techniques

Lecture 1 Need for Testing

Objectives of Testing Test Categories

Why Testing?
Testing is one of the most expensive parts of chips
Logic verification accounts for > 50% of design effort for many chips Debug time after fabrication has enormous opportunity cost Shipping defective parts can sink a company

Example: Intel FDIV bug

Logic error not caught until > 1M units shipped Recall cost $450M (!!!)

Why Testing?
Yield = Number of good die / Total number of die per wafer. Because of the complexity of the manufacturing process, not all die on a wafer function correctly. Dust particles and small imperfections in starting material or photo masking can result in a bridged connections or missing features and these imperfections are called faults. Testing a chip can occur at
Wafer level Packaged chip level Board level System level Field level.

Why Testing?
By detecting a malfunctioning chip early, the manufacturing cost can be kept low. The approximate cost to a company of detecting a fault at the various levels is

Level Wafer Level Packaged Chip Level Board Level System Level Field Level

Approximate Cost $0.01 - $0.10 $0.10 - $1 $1 - $10 $10 - $100 $100 - $1000

Testing at Various Levels

Objectives of Testing
Two primary objectives
Fault Detection & Fault location

Fault Any condition that causes a device to function improperly. Fault Detection Testing
The process of determining whether or nor a fault is present in a given device. A set of inputs to a circuit that can be used to detect a fault in the circuit is a Fault Detection Test Set (FDTS)

Fault Location Testing

The process of determining which fault is present in a faulty device. A set of inputs that can be used to locate a fault is a Fault Location Test Set (FLTS)

Test Categories
Functionality Tests (Logical Verification)
Silicon Debug Manufacturing Tests

Logical Verification
Does the chip simulate correctly?
Usually done at HDL level Verification engineers write test bench for HDL
Cant test all cases Look for corner cases Try to break logic design

Ex: 32-bit adder

Test all combinations of corner cases as inputs: 0, 1, 2, 231-1, -1, -231, a few random numbers

Silicon Debug
Confirm that the chip operates as it was intended and help debug any discrepancies.

Run on the first batch of the chips that return from the fabrication.
If you are lucky, they work the first time, If not???

Much more extensive than the first one because the chip can be tested at a full speed in a system.
Required to locate the cause of failures because the designer has less visibility into the fabricated chip compared to during design verification.

Silicon Debug
Logic bugs vs. electrical failures
Most chip failures are logic bugs from inadequate simulation Some are electrical failures
Crosstalk Dynamic nodes: leakage, charge sharing Ratio failures

A few are tool or methodology failures (e.g. DRC)

Fix the bugs and fabricate a corrected chip

Manufacturing Tests
Verify that every transistor, gate and storage element in the chip functions correctly. Conducted on the manufactured chip before shipping to the customer to verify that the silicon is completely intact. A speck of dust on a wafer is sufficient to kill chip Yield of any chip is < 100%
Must test chips after manufacturing before delivery to customers to only ship good parts

Manufacturing Tests
Manufacturing testers are very expensive
Minimize time on tester Careful selection of test vectors

Same tests can be used for all three steps It is easier to use one set of tests to chase down the logic bugs and another, separate set optimized for manufacturing defects.

Lecture 2 Manufacturing Test Principles

Fault Models Observability & Controllability Fault Coverage Automatic Test Pattern Generation (ATPG) Delay Fault Testing

Combinational Circuit Testing

Types of Faults
Fault Any condition that causes a device to function improperly. Solid or Permanent Fault
A faulty condition that does not change with time.

Intermittent Fault
A faulty condition that appears and disappears with time.

Logical Faults
Faults that cause a given logical device to function entirely different logic device.

Non Logical Faults

All faults other than logical faults

Stuck-at Fault Model

A popular and useful model for representing faults in the logic device. Types of model
Stuck-at logic zero (s-a-0) Stuck-at logic one (s-a-1)

These faults are due to

Gate oxide shorts Metal-to-metal shorts

Short-Circuit Faults
Other Names: Stuckclosed faults or Bridging faults The short S1 results in an S-A-0 fault at input A The short S2 modifies the function of the gate. To ensure the most accurate modeling, faults should be modeled at the transistor level because the complete circuit structure is known only at this level.

Identifying Stuck-closed Faults

By observing static current (IDD) while applying test vectors A 2-input NOR gate Fault The drain connection on a pMOS transistor is shorted to VDD. This fault occurs due to the overlapping of stray metal on the VDD line and drain connections. Identifying the faults
Apply the test vectors 01 or 10 to the A and B inputs Measure the static IDD Notice that it rises to some value determined by size of the nMOS transistors.

Open Circuit Faults

Convert a combinational logic circuit into a sequential logic circuit. A 2-input NOR gate. One of the transistors rendered is ineffective. If the nMOS transistor A is stuck open, then the function displayed by the gate will be
Z = A + B + B Z'

where Z is the previous state of the gate.

Observability & Controllability

Observability
Ease of observing a node by watching external output pins of the chip

Controllability
Ease of forcing a node to 0 or 1 by driving input pins of the chip

Combinational logic is usually easy to observe and control Finite state machines can be very difficult, requiring many cycles to enter desired state
Especially if state transition diagram is not known to the test engineer

To increase Testability
Increase Observability
Add more pins (?!)

Add small probe bus, selectively enable different values onto bus
Use a hash function to compress a sequence of values (e.g., the values of a bus over many clock cycles) into a small number of bits for later read read-out Cheap read read-out of all state information

Increase Controllability
Use muxes to isolate sub sub-modules andselect sources of test data as inputs
Provide easy setup of internal state

Fault Coverage
A measure of goodness of a set of test vectors.
What percentage of the chips internal nodes were checked? Should be excess of 98.5% fault coverage.

Procedure
Take each circuit node in sequence. Held to 0 (S-A-0) Identify the faults Held to 1 (S-A-1) Identify the faults
Total nodes detected as faulty Fault Coverage =

Test vectors applied

Test Pattern Generation

Manufacturing test ideally would check every node in the circuit to prove it is not stuck. Apply the smallest sequence of test vectors necessary to prove each node is not stuck. Good Observability and controllability reduces number of test vectors required for manufacturing test.
Reduces the cost of testing Motivates design-for-test

Automatic Test Pattern Generation (ATPG)

For given fault, determine excitation vector (called test vector) that will propagate error to primary (observable) output. Majority of available tools: combinational networks only Sequential ATPG available from academic research.

Automatic Test Pattern Generation (ATPG)

Most ATPG approaches have been based on simulation. A five vale logic is used to implement test generation algorithms 1 0 X D D Logic One Logic Zero Unknown or Dont Care Condition Logic 1 in good machine. Logic 0 in faulty machine Logic 0 in good machine. Logic 1 in faulty machine

Automatic Test Pattern Generation (ATPG)

Truth Table for Inverter A 0 1 X D D Z 1 0 X D D

Automatic Test Pattern Generation (ATPG)

Truth Table for 2-inpt AND gate

A\B 0 1 X D D

0 0 0 0 0 0

1 0 1 X D D

X 0 X X X X

D 0 D X D 0

D 0 D X 0 D

Automatic Test Pattern Generation (ATPG)

Truth Table for 2-inpt OR gate

A\B 0 1 X D D

0 0 0 X D D

1 1 1 1 1 1

X X 1 X X X

D D 1 X D 1

D D 1 X 1 D

Delay Fault Testing

Timing is also included. Still works with increased tpdf. Fault become sequential as the detection of the fault depends on the previous state of the gate. Occurs due to crosstalk. Occurs in SOI due to history effect.

Fault Sampling
Used in circuits where it is impossible to fault every node in the circuit. Nodes are randomly selected and faulted. The resulting fault detection rate may be statistically inferred from the number of faults that are detected in the fault set and size of the set. It is important that the randomly selected faults be unbiased. This approach does not yield specific level of fault coverage but it will determine whether the fault coverage exceeds a desired level. The level of confidence may be increased by increasing the number of samples.

Lecture 3 Design Strategies for Test

Design for Testability Ad hoc Testing Scan Based Test Techniques Self Test Techniques IDDQ Testing

Design For Testability (DFT)

Two concepts
Controllability & Observability

Design for Testability

Ad hoc testing Scan based approaches Self test and built-in testing

Adhoc Testing
Ad Ad-hoc test techniques are a collection of ideas aimed at reducing the test time. Common techniques are:
Partitioning large sequential circuits Adding test points Adding multiplexers Providing for easy state access

Adhoc Testing

Adhoc Testing
Bus Oriented technique

Adhoc Testing
Multiplexer based testing

Scan Design
To provide observability & controllability to each register.

Convert each flip-flop to a scan register

Only costs one extra multiplexer

Normal mode: flip-flops behave as usual Scan mode: flip-flops behave as shift register

Contents of flops can be scanned out and new values scanned in.

Scan Design

Scan Design Serial Scan

Scan Design Parallel Scan

Built in Self Test (BIST)

BIST lets blocks test themselves.
Generate pseudo-random inputs to combinational logic. Combine outputs into a syndrome. With high probability, block is fault-free if it produces the expected syndrome

Rapidly becoming more important with increasing chip-complexity and larger modules

Built in Self Test (BIST)

Pseudo Random Sequence Generator (PRSG)

Linear Feedback Shift Register Shift register with input taken from XOR of state Step 0 1 2 3 4 5 6 7 Q 111 110 101 010 100 001 011 111

Pseudo Random Sequence Generator (PRSG)

IDDQ Testing
A method of detecting bridging faults (shorts). CMOS logic should draw no current when its not switching. When a bridging fault occurs, for some combination of the input, a measurable IDD flows.

IDDQ Testing
Testing Sequence
Apply normal vectors Allow the signals to settle Measure IDD.

Suitable for testing only one gate High test time IDDQ testing can be performed
Externally to the chip by measuring the current drawn on the VDD line Internally using specially constructed test vectors.

Lecture 4 Chip Level Test Techniques

Regular Logic Arrays Memories Random Logic

Regular Logic Arrays

Parallel Scan or Series Scan Input busses may be driven by a serially loaded register. These in turn may be used to load the internal data path registers. These data path registers may be sourced onto a bus, and this bus may be loaded into a register that may be serially accessed. All of the control signals to the data path are also made scannable.

Memories
Use self testing techniques. Alternatively, the provision of multiplexers on data inputs and addresses and convenient external access to data outputs enables the testing of embedded memories. It is a mistake to have memories indirectly accessible. Because memories have to tested exhaustively and any overhead on writing and reading the memories can substantially increase the test time.

Random Logic
Probably best tested via full serial scan or parallel scan.

Lecture 5 System (Board) Level Test Techniques

Boundary Scan

Boundary Scan
System (Board) Level Defects
Open and shorted PCB traces and incomplete solder joints.

Bed-of-nails Testers
At the board level, chips obeying the standard may be connected in a variety of series and parallel combinations for board testing (replacing bead of nails)

The IEEE 1149.1 boundary scan architecture provides a standardized serial scan path through the I/O pins of a chip (also called JTAG Joint Test Access Group)

Boundary Scan Architecture

Boundary Scan
All the I/O pins are connected serially in a standardized chain accessed through the Test Access Port (TAP). Every pin can be observed and controlled remotely through the scan chain. Standardized tests:
Connectivity tests between components Sampling and setting chip I/Os Distribution an collection of self self-test or built-in test results

Test Access Port (TAP)

TAP has four or five single-bit connections.
TCK
TMS TDI TDO TRST (optional) Test Clock Test Mode Select

Input
Input

Clocks tests into and out of the chip Controls test operations Test Data into the chip Test data out of the chip. Driven only when TAP controller is shifting out test data . Reset the TAP controller if no reset signal is generated automatically by the chip.

Test Input Data In

Test Data Out Test Reset Output

Input

Test Access Port (TAP)

Test Access Port (TAP)

It consists of
TAP Interface Pins A set of two or more test-data registers (DR) to collect data from the chip. An instruction register (IR) specifying the type of test to perform. A TAP controller, which controls the scan bits through the instruction and test-data registers

Two modes of operation

It scans an instruction into the IR specifying what boundary scan should do It scan data in and out of the DR.

Test Access Port

The specification requires at least two test-data registers.
Boundary Scan Register
Associated with all the inputs and outputs on the chip so that boundary scan can observe and control the chip I/Os.

Bypass Registers
A single FF used to accelerate testing by avoiding shifting data into the boundary scan registers of idle chips when only a single chip on the board is being tested.

Internal Scan Chain or BIST are optional additional DRs.

TAP Controller

TAP Controller
A 16-state FSM that proceeds from state to state based on the TCK and TMS signals. It provides signals that control the DR and IR. It is initialized to Test-Logic-Reset by TRST or by internal signal. It moves from one state to the next state on the rising edge of the TCK signal based on TMS. Typical test sequence
Give TCK - Perform TRST Give TCK - Perform operation based on TMS

Operations
Serially loading IR Serially loading or reading DR

Instruction Registers
At least two bits long. Boundary scan requires at least two DRs. IR specifies which DR will be placed in the scan chain when the DR is selected. IR determines where the DR will load its value from in the Capture-DR state and whether the values will be driven to output pads or core logic.

Instruction Registers
The following instructions are required
BYPASS Places the Bypass Register in the DR chain so that the path from TDI to TDO involves only by a single FF. Allows specific chips to be tested in a serial scan chain. Represented with all 1s in the IR.

SAMPLE/PR Places the Boundary Scan Register in the DR chain ELOAD In Capture-DR state, it copies the I/O values into DRs. EXTEST Allows for the testing of off-chip circuitry. Similar to SAMPLE/PREOAD, but also drives values from DRs on to the output pads. Allows a single step testing of internal circuitry via boundary scan registers. Used to activate internal self testing procedures within a chip.

INTEST (optional) RUNBIST (optional)

Instruction Registers
A typical IR bit is shown in figure.
In the Capture-IR state, data is given and then shifted out in the shift-IR when new vales are shifted in. In the Update-IR state, the contents of shift register are copied in parallel to the IR output to load the entire instruction at once.

Data Registers

Data Registers
Used to set the inputs of the modules to be tested and collect the results of running tests. Consists of boundary scan register and a bypass register. Represents the scan chain within the chip. MUX selects which DR is routed to the TDO pin. When internal DRs are added, the IR decoder must produce extra control signals to select which one is in the DR chain for the particular instruction.

Boundary Scan Register

Boundary Scan Register

Connects all the I/O circuitry. Consists of a shift register for the scan chain and an additional bank of FFs to update the outputs in parallel. MUX allows to override the normal path through the I/O pad. Can be configured as input or output.

Bypass Register
When executing the BYPSS instruction, the single-bit bypass register is connected between TDI & TDO. A single FF, cleared during Capture-DR and Scanned during Shift-DR.

TDO Driver
TDO pin shifts out the LSB of IR during Shift-IR or the LSB of DR during Shift-DR. TDO change on the falling edge of the TCK. Multiplexers choose among instruction register, boundary scan register or bypass register.

Complete Boundary Scan Implementation

Complete Boundary Scan Implementation

A complete boundary scan for a chip with
4 inputs {a[1], a[2], a[3], a[4]} and 4 outputs {y[1], y[2], y[3], y[4]}.

It consists of
TAP controller state machine & state controller A 3-bit IR with instruction decode. Bypass register 4 boundary scan output pads.

Queries ?????
vlsinathan@rediffmail.com