Crystal Growth Techniques

Polycrystalline silicon has randomly oriented crystallites electrical characteristics are not ready for device fabrication Convert EGS grade polysilicon into single crystal silicon
High Temperature Single crystal silicon seed as template

Commonly used Methods

Bridgman Method Czochralski Method Float zone Method

Bridgman Method
Evacuated and sealed silica ampoule Quartz boat carrying seed crystal and charge (powdered high purity EGS polysilicon Charge alone is heated to melting point Heating mechanism

Bridgman Method
Requires seed crystal. Directional solidification. Precise temperature gradient only the charge should melt not the seed crystal.

Bridgman Method
Drawbacks
Si expands on cooling. As it starts to cool, the confining boundary of quartz boat excretes a shearing stress leading to crystal dislocations. Contamination from boat Difficult to make round wafers in horizontal furnace

Czochralski Method
EGS melted in slowly rotating quartz crucible at 1415C It consist of:
Furnace Crystal pulling mechanism Ambient control Control systems

Czochralski Method
Single crystal silicon seed is mounted on a slowly rotating chuck and lowered into the molten silicon. Portion of the seed crystal which is in contact with the molten Si begins to melt. However the seed crystal temperature is precisely controlled to be just below that of molten Si.

Raw materials (SiO2) are refined to produce electronic grade silicon with a purity unmatched by any other commonly available material on earth. CZ crystal growth produces structurally perfect Si single crystals which can then be cut into wafers and polished as the starting material for IC manufacturing. Starting wafers contain only dopants, O, and C in measurable quantities. Dopant incorporation during crystal growth is straightforward except for segregation effects which cause spatial variations in the dopant concentrations. Point, line, and volume (1D, 2D, and 3D) defects can be present in crystals, particularly after high temperature processing. Point defects are "fundamental" and their concentration depends on temperature (exponentially), on doping level and on other processes like ion implantation which can create non-equilibrium transient concentrations of these defects.

Clean room, wafer cleaning and gettering

3 tiered approach
1. clean factories 2. wafer cleaning 3. gettering

3 Level control
Level 1 control - clean factories through air filtration and highly purified chemicals and gases. Level 2 control - wafer cleaning using basic chemistry to remove unwanted elements from wafer surfaces. Level 3 control - gettering to collect metal atoms in regions of the wafer far away from active devices.

Contaminants may consist of particles, organic films (photoresist), heavy metals or alkali ions.

Particles

Na

Cu Photoresist N, P

Fe

Au

S iO2 or other thin films

Interconnect Metal S ilicon Wafer

Year of Production Te chnology N ode (half pi tch) MPU Printed Gate Length D RAM Bits/Chip (Sampli ng) MPU Transistors/Chip (x106) Critical Defect Size Starting Wafer Particles (cm -2 ) Starting Wafer Total Bulk Fe (cm -3 ) Me tal Atom s on Wafer Surface After Cleaning (cm -2 ) Particles on Wafer Surface After Cleaning (#/ wa fer)

1998

2000

2002 130 nm 70 nm 1G

2004 90 nm 53 nm 4G 550

2007 65 nm 35 nm 16G 1100 90 nm <0.18 1x1010 1x1010

2010 45 nm 25 nm 32G 2200 90 nm <0.09 1x1010 1x1010

2013 32 nm 18 nm 64G 4400 65 nm <0.09 1x1010 1x1010

2016 22 nm 13 nm 128G 8800 45 nm <0.05 1x1010 1x1010

2018 18 nm 10 nm 128G 14,000 45 nm <0.05 1x1010 1x1010

250 nm 180 nm 100 nm 256M 512M

125 nm

90 nm

90 nm

90 nm <0.35

3x1010 5x109

1x1010 1x1010

1x1010 1x1010

1x1010 1x1010

75

80

86

195

106

168

Level 1 Contamination Reduction: Clean Factories

1 07 1 06 1 05 1 04 1000 100 10 1 0.1 1 10 Particle Size (m) 100 1
.

100,000 10,000 1000 100 10

Air quality is measured by the class of the facility.

T o t a l P a r t i c l e s P e r C u b i c F o o t

Factory environment is cleaned by: HEPA (High Efficiency Particulate Air) filters and recirculation for the air, Bunny suits for workers. Filtration of chemicals and gases. Manufacturing protocols.

(Photo courtesy of Stanford Nanofabrication Facility.)

Level 2 Contamination Reduction: Wafer Cleaning

H2SO4/H2O2 1:1 to 4:1 120 - 150C 10 min Strips organics especially photoresist

HF/H 2O 1:10 to 1:50

Room T 1 min

Strips chemical oxide

DI H2O Rinse

Room T

NH4OH/H 2O2/H2O 1:1:5 to 0.05:1:5 SC-1

80 - 90C 10 min

Strips organics, metals and particles

DI H2O Rinse

Room T

HCl/H 2O2/H 2O 1:1:6 SC-2

80 - 90C 10 min

Strips alkali ions and metals

RCA clean is standard process used to remove organics, heavy metals and alkali ions.

DI H2O Rinse

Room T

Ultrasonic agitation is used to dislodge particles.

Level 3 Contamination Reduction: Gettering

Gettering is used to remove metal ions and alkali ions from device active regions.
P eriod

1 2 3 4 5 6 7

Shallow Acceptors

For metal ions, gettering generally uses traps on the wafer backside or in the wafer bulk. Backside = extrinsic gettering. Bulk = intrinsic gettering.

Elemental Semiconductors Shallow Donors

H 1.008 3 Li 6.941 11 Na 22.99 19 K 39.10 37 Rb 85.47 55 Cs 132.9 87 Fr 223

IA
4

Alkali Ions II
A

Noble Gases

III A IV A V
B Deep Level Impurites in S ilicon 10.81 13 VIII Al B B B B B 26.98 V VI VII I II 23 24 25 26 28 29 30 31 27 V Cr Mn Fe Co Ni Cu Zn Ga 50.94 51.99 54.94 55.85 58.93 58.69 63.55 65.39 69.72 41 42 43 44 45 46 47 48 49 Nb Mo Tc Ru Rh Pd Ag Cd In 92.91 95.94 98 101.1 102.9 106.4 107.9 112.4 114.8 73 74 75 76 77 78 79 80 81 Ta W Re Os Ir Pt Au Hg Tl 180.8 183.9 186.2 190.2 192.2 195.1 197.0 200.6 204.4 105 106 107 Unp Unh Uns 262 263 262 5 C 12.01 14 Si 28.09 32 Ge 72.59 50 Sn 118.7 82 Pb 207.2 6 7

VI A VII A
O 16.00 16 S 32.06 34 Se 78.96 52 Te 127.6 84 Po 209 8 F 19.00 17 Cl 35.45 35 Br 79.90 53 I 126.9 85 At 210 9

Be 9.012 12 Mg 24.31 20 Ca 40.08 38 Sr 87.62 56 Ba 137.3 88 Ra 226

21 Sc 44.96 39 Y 88.91 57 La 138.9 89 Ac 227.0

III

22 Ti 47.88 40 Zr 91.22 72 Hf 178.5 104 Unq 261

IV

N 14.01 15 P 30.97 33 As 74.92 51 Sb 121.8 83 Bi 209.0

2 He 4.003 10 Ne 20.18 18 Ar 39.95 36 Kr 83.80 54 Xe 131.3 86 Rn 222

PSG Layer Devices in near surface region Denude d Zone or Epi Layer

10 - 20 m

Intrinsic Gettering Region

500+ m

Backside Gettering Region

Heavy metal gettering relies on: Metals diffusing very rapidly in silicon. Metals segregating to trap sites.

 Gettering consists of 1. Making metal atoms mobile. 2. Migration of these atoms to trapping sites. 3. Trapping of atoms. Step 1 generally happens by kicking out the substitutional atom into an interstitial site. One possible reaction is: Au S I Au i Step 2 usually happens easily once the metal is interstitial since most metals diffuse rapidly in this form. Step 3 happens because heavy metals segregate preferentially to damaged regions or to N+ regions or pair with effective getters like P (AuP pairs). (See text.) In intrinsic gettering, the metal atoms segregate to dislocations around SiO2 precipitates.

three-tiered approach is used to minimize contamination in wafer processing.

Particle control, wafer cleaning and gettering are some of the "nuts and bolts" of chip manufacturing.
The economic success (i.e. chip yields) of companies manufacturing chips today depends on careful attention to these issues. Level 1 control - clean factories through air filtration and highly purified chemicals and gases. Level 2 control - wafer cleaning using basic chemistry to remove unwanted elements from wafer surfaces.

Level 3 control - gettering to collect metal atoms in regions of the