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Polycrystalline silicon has randomly oriented crystallites electrical characteristics are not ready for device fabrication Convert EGS grade polysilicon into single crystal silicon
High Temperature Single crystal silicon seed as template
Bridgman Method
Evacuated and sealed silica ampoule Quartz boat carrying seed crystal and charge (powdered high purity EGS polysilicon Charge alone is heated to melting point Heating mechanism
Bridgman Method
Requires seed crystal. Directional solidification. Precise temperature gradient only the charge should melt not the seed crystal.
Bridgman Method
Drawbacks
Si expands on cooling. As it starts to cool, the confining boundary of quartz boat excretes a shearing stress leading to crystal dislocations. Contamination from boat Difficult to make round wafers in horizontal furnace
Czochralski Method
EGS melted in slowly rotating quartz crucible at 1415C It consist of:
Furnace Crystal pulling mechanism Ambient control Control systems
Czochralski Method
Single crystal silicon seed is mounted on a slowly rotating chuck and lowered into the molten silicon. Portion of the seed crystal which is in contact with the molten Si begins to melt. However the seed crystal temperature is precisely controlled to be just below that of molten Si.
Raw materials (SiO2) are refined to produce electronic grade silicon with a purity unmatched by any other commonly available material on earth. CZ crystal growth produces structurally perfect Si single crystals which can then be cut into wafers and polished as the starting material for IC manufacturing. Starting wafers contain only dopants, O, and C in measurable quantities. Dopant incorporation during crystal growth is straightforward except for segregation effects which cause spatial variations in the dopant concentrations. Point, line, and volume (1D, 2D, and 3D) defects can be present in crystals, particularly after high temperature processing. Point defects are "fundamental" and their concentration depends on temperature (exponentially), on doping level and on other processes like ion implantation which can create non-equilibrium transient concentrations of these defects.
3 tiered approach
1. clean factories 2. wafer cleaning 3. gettering
3 Level control
Level 1 control - clean factories through air filtration and highly purified chemicals and gases. Level 2 control - wafer cleaning using basic chemistry to remove unwanted elements from wafer surfaces. Level 3 control - gettering to collect metal atoms in regions of the wafer far away from active devices.
Contaminants may consist of particles, organic films (photoresist), heavy metals or alkali ions.
Particles
Na
Cu Photoresist N, P
Fe
Au
Year of Production Te chnology N ode (half pi tch) MPU Printed Gate Length D RAM Bits/Chip (Sampli ng) MPU Transistors/Chip (x106) Critical Defect Size Starting Wafer Particles (cm -2 ) Starting Wafer Total Bulk Fe (cm -3 ) Me tal Atom s on Wafer Surface After Cleaning (cm -2 ) Particles on Wafer Surface After Cleaning (#/ wa fer)
1998
2000
2002 130 nm 70 nm 1G
2004 90 nm 53 nm 4G 550
125 nm
90 nm
90 nm
90 nm <0.35
3x1010 5x109
1x1010 1x1010
1x1010 1x1010
1x1010 1x1010
75
80
86
195
106
168
T o t a l P a r t i c l e s P e r C u b i c F o o t
Factory environment is cleaned by: HEPA (High Efficiency Particulate Air) filters and recirculation for the air, Bunny suits for workers. Filtration of chemicals and gases. Manufacturing protocols.
Room T 1 min
DI H2O Rinse
Room T
80 - 90C 10 min
DI H2O Rinse
Room T
80 - 90C 10 min
RCA clean is standard process used to remove organics, heavy metals and alkali ions.
DI H2O Rinse
Room T
1 2 3 4 5 6 7
Shallow Acceptors
For metal ions, gettering generally uses traps on the wafer backside or in the wafer bulk. Backside = extrinsic gettering. Bulk = intrinsic gettering.
IA
4
Alkali Ions II
A
Noble Gases
III A IV A V
B Deep Level Impurites in S ilicon 10.81 13 VIII Al B B B B B 26.98 V VI VII I II 23 24 25 26 28 29 30 31 27 V Cr Mn Fe Co Ni Cu Zn Ga 50.94 51.99 54.94 55.85 58.93 58.69 63.55 65.39 69.72 41 42 43 44 45 46 47 48 49 Nb Mo Tc Ru Rh Pd Ag Cd In 92.91 95.94 98 101.1 102.9 106.4 107.9 112.4 114.8 73 74 75 76 77 78 79 80 81 Ta W Re Os Ir Pt Au Hg Tl 180.8 183.9 186.2 190.2 192.2 195.1 197.0 200.6 204.4 105 106 107 Unp Unh Uns 262 263 262 5 C 12.01 14 Si 28.09 32 Ge 72.59 50 Sn 118.7 82 Pb 207.2 6 7
VI A VII A
O 16.00 16 S 32.06 34 Se 78.96 52 Te 127.6 84 Po 209 8 F 19.00 17 Cl 35.45 35 Br 79.90 53 I 126.9 85 At 210 9
III
IV
PSG Layer Devices in near surface region Denude d Zone or Epi Layer
10 - 20 m
500+ m
Heavy metal gettering relies on: Metals diffusing very rapidly in silicon. Metals segregating to trap sites.
Gettering consists of 1. Making metal atoms mobile. 2. Migration of these atoms to trapping sites. 3. Trapping of atoms. Step 1 generally happens by kicking out the substitutional atom into an interstitial site. One possible reaction is: Au S I Au i Step 2 usually happens easily once the metal is interstitial since most metals diffuse rapidly in this form. Step 3 happens because heavy metals segregate preferentially to damaged regions or to N+ regions or pair with effective getters like P (AuP pairs). (See text.) In intrinsic gettering, the metal atoms segregate to dislocations around SiO2 precipitates.
Particle control, wafer cleaning and gettering are some of the "nuts and bolts" of chip manufacturing.
The economic success (i.e. chip yields) of companies manufacturing chips today depends on careful attention to these issues. Level 1 control - clean factories through air filtration and highly purified chemicals and gases. Level 2 control - wafer cleaning using basic chemistry to remove unwanted elements from wafer surfaces.