EE105 Fall 2007 Lecture 21, Slide 1 Prof.

Liu, UC Berkeley
Lecture 21
OUTLINE
Frequency Response
Review of basic concepts
high-frequency MOSFET model
CS stage
CG stage
Source follower
Cascode stage
Reading: Chapter 11
REMINDERS
Review session: Fri. 11/9, 3-5PM in 306 Soda (HP Auditorium)
Midterm #2 (Thursday 11/15, 3:30-5PM in Sibley Auditorium)
EE105 Fall 2007 Lecture 21, Slide 2 Prof. Liu, UC Berkeley
The impedance of C
L
decreases at high frequencies, so
that it shunts some of the output current to ground.






In general, if node j in the signal path has a small-
signal resistance of R
j
to ground and a capacitance C
j
to
ground, then it contributes a pole at frequency (R
j
C
j
)
-1
A
v
Roll-Off due to C
L

L D
p
C R
1
= e
0 =
|
|
.
|

\
|
=
L
D m v
C j
R g A
e
1
||
EE105 Fall 2007 Lecture 21, Slide 3 Prof. Liu, UC Berkeley
Pole Identification Example 1
in G
p
C R
1
1
= e
L D
p
C R
1
2
= e
0 =
EE105 Fall 2007 Lecture 21, Slide 4 Prof. Liu, UC Berkeley
Pole Identification Example 2
in
m
G
p
C
g
R
|
|
.
|

\
|
=
1
||
1
1
e
L D
p
C R
1
2
= e
0 =
EE105 Fall 2007 Lecture 21, Slide 5 Prof. Liu, UC Berkeley
Dealing with a Floating Capacitance
Recall that a pole is computed by finding the resistance
and capacitance between a node and (AC) GROUND.
It is not straightforward to compute the pole due to C
F

in the circuit below, because neither of its terminals is
grounded.
EE105 Fall 2007 Lecture 21, Slide 6 Prof. Liu, UC Berkeley
Millers Theorem
If A
v
is the voltage gain from node 1 to 2, then a
floating impedance Z
F
can be converted to two
grounded impedances Z
1
and Z
2
:
v
F F
F
A
Z
V V
V
Z Z
Z
V
Z
V V

= =

1
1

2 1
1
1
1
1 2 1
v
F F
F
A
Z
V V
V
Z Z
Z
V
Z
V V
1
1
1

2 1
2
2
2
2 2 1

= =

EE105 Fall 2007 Lecture 21, Slide 7 Prof. Liu, UC Berkeley

Miller Multiplication
Applying Millers theorem, we can convert a floating
capacitance between the input and output nodes of
an amplifier into two grounded capacitances.
The capacitance at the input node is larger than the
original floating capacitance.
( )
F v v
F
v
F
C A j A
C j
A
Z
Z

=
1
1
1
1
1
1
e
e
F
v
v
F
v
F
C
A
j
A
C j
A
Z
Z
|
.
|

\
|

=

=
1
1
1
1
1
1
1
1
2
e
e
EE105 Fall 2007 Lecture 21, Slide 8 Prof. Liu, UC Berkeley
Application of Millers Theorem
( )
F D m G
in
C R g R +
=
1
1
e
F
D m
D
out
C
R g
R
|
|
.
|

\
|
+
=
1
1
1
e
0 =
EE105 Fall 2007 Lecture 21, Slide 9 Prof. Liu, UC Berkeley
MOSFET Intrinsic Capacitances
The MOSFET has intrinsic capacitances which affect its
performance at high frequencies:
1. gate oxide capacitance between the gate and channel,
2. overlap and fringing capacitances between the gate and the
source/drain regions, and
3. source-bulk & drain-bulk junction capacitances (C
SB
& C
DB
).
EE105 Fall 2007 Lecture 21, Slide 10 Prof. Liu, UC Berkeley
High-Frequency MOSFET Model
The gate oxide capacitance can be decomposed into a
capacitance between the gate and the source (C
1
) and
a capacitance between the gate and the drain (C
2
).
In saturation, C
1
~ (2/3)C
gate
, and C
2
~ 0.
C
1
in parallel with the source overlap/fringing capacitance C
GS
C
2
in parallel with the drain overlap/fringing capacitance C
GD
EE105 Fall 2007 Lecture 21, Slide 11 Prof. Liu, UC Berkeley
Example
CS stage
with MOSFET capacitances
explicitly shown
Simplified circuit for
high-frequency analysis
EE105 Fall 2007 Lecture 21, Slide 12 Prof. Liu, UC Berkeley
Transit Frequency
GS
m
T
C
g
f = t 2
The transit or cut-off frequency, f
T
, is a measure
of the intrinsic speed of a transistor, and is defined as
the frequency where the current gain falls to 1.
Conceptual set-up to measure f
T
in
m
T
in T
m in m
in
out
C
g
C j
g Z g
I
I
=
=
|
|
.
|

\
|
= =
e
e
1
1
in
in
in
Z
V
I =
in m out
V g I =
EE105 Fall 2007 Lecture 21, Slide 13 Prof. Liu, UC Berkeley
Small-Signal Model for CS Stage
0 =
EE105 Fall 2007 Lecture 21, Slide 14 Prof. Liu, UC Berkeley
Applying Millers Theorem
( ) ( )
GD D m in Thev
in p
C R g C R + +
=
1
1
,
e
|
|
.
|

\
|
|
|
.
|

\
|
+ +
=
GD
D m
out D
out p
C
R g
C R
1
1
1
,
e
Note that e
p,out
> e
p,in
EE105 Fall 2007 Lecture 21, Slide 15 Prof. Liu, UC Berkeley
Direct Analysis of CS Stage
Direct analysis yields slightly different pole locations
and an extra zero:
( ) ( )
( ) ( )
( )
out in XY out XY in D Thev
out XY D in Thev Thev XY D m
p
out XY D in Thev Thev XY D m
p
XY
m
z
C C C C C C R R
C C R C R R C R g
C C R C R R C R g
C
g
+ +
+ + + +
=
+ + + +
=
=
1
1
1
2
1
e
e
e
EE105 Fall 2007 Lecture 21, Slide 16 Prof. Liu, UC Berkeley
I/O Impedances of CS Stage
( ) | |
GD D m GS
in
C R g C j
Z
+ +
~
1
1
e | |
D
DB GD
out
R
C C j
Z ||
1
+
=
e
0 =
EE105 Fall 2007 Lecture 21, Slide 17 Prof. Liu, UC Berkeley
CG Stage: Pole Frequencies
X
m
S
X p
C
g
R
|
|
.
|

\
|
=
1
||
1
,
e
SB GS X
C C C + =
Y D
Y p
C R
1
,
= e
DB GD Y
C C C + =
CG stage with MOSFET capacitances shown
0 =
EE105 Fall 2007 Lecture 21, Slide 18 Prof. Liu, UC Berkeley
AC Analysis of Source Follower
The transfer function of a
source follower can be
obtained by direct AC
analysis, similarly as for
the emitter follower (ref.
Lecture 14, Slide 6)
( )
( ) ( ) 1
1
2
+ +
+
=
e e
e
j b j a
g
C
j
v
v
m
GS
in
out
( )
m
SB GD
GD S
SB GS SB GD GS GD
m
S
g
C C
C R b
C C C C C C
g
R
a
+
+ =
+ + =
0 =
EE105 Fall 2007 Lecture 21, Slide 19 Prof. Liu, UC Berkeley
Example
| |
1
2 2 1 1
1
2 2 1 1 1 1 1
1
) )( (
m
DB GD SB GD
GD S
DB GD SB GS GD GS GD
m
S
g
C C C C
C R b
C C C C C C C
g
R
a
+ + +
+ =
+ + + + =
( )
( ) ( ) 1
1
2
+ +
+
=
e e
e
j b j a
g
C
j
v
v
m
GS
in
out
EE105 Fall 2007 Lecture 21, Slide 20 Prof. Liu, UC Berkeley
Source Follower: Input Capacitance
S m
GS
GD in
R g
C
C C
+
+ =
1
Recall that the voltage gain of a source follower is
S
m
S
v
R
g
R
A
+
=
1
Follower stage with MOSFET capacitances shown
0 =
( )
S m
GS
GS v X
R g
C
C A C
+
= =
1
1
C
XY
can be decomposed into
C
X
and C
Y
at the input and
output nodes, respectively:
EE105 Fall 2007 Lecture 21, Slide 21 Prof. Liu, UC Berkeley
Example
( )
1
2 1 1
1
|| 1
1
GS
O O m
GD in
C
r r g
C C
+
+ =
0 =
EE105 Fall 2007 Lecture 21, Slide 22 Prof. Liu, UC Berkeley
Source Follower: Output Impedance
m GS
GS G
X
X
g C j
C R j
i
v
+
+
=
e
e 1
The output impedance of
a source follower can be
obtained by direct AC
analysis, similarly as for
the emitter follower (ref.
Lecture 14, Slide 9)
0 =
EE105 Fall 2007 Lecture 21, Slide 23 Prof. Liu, UC Berkeley
Source Follower as Active Inductor
CASE 1: R
G
< 1/g
m
CASE 2: R
G
> 1/g
m
A follower is typically used to lower the driving impedance,
i.e. R
G
is large compared to 1/g
m,
so that the active inductor
characteristic on the right is usually observed.
m GS
GS G
out
g C j
C R j
Z
+
+
=
e
e 1
EE105 Fall 2007 Lecture 21, Slide 24 Prof. Liu, UC Berkeley
Example
( )
3 3
3 2 1
1 ||
m GS
GS O O
out
g C j
C r r j
Z
+
+
=
e
e
0
3
=
EE105 Fall 2007 Lecture 21, Slide 25 Prof. Liu, UC Berkeley
MOS Cascode Stage
For a cascode stage, Miller multiplication is smaller
than in the CS stage.
1
1
2
1 ,
~
|
|
.
|

\
|
=
m
m
Y
X
XY v
g
g
v
v
A
XY X
C C 2 ~
EE105 Fall 2007 Lecture 21, Slide 26 Prof. Liu, UC Berkeley
Cascode Stage: Pole Frequencies
(

|
|
.
|

\
|
+ +
=
1
2
1
1
,
1
1
GD
m
m
GS G
X p
C
g
g
C R
e
(

+
|
|
.
|

\
|
+ + +
=
2 1
1
2
2 1
2
,
1
1
1
SB GD
m
m
GS DB
m
Y p
C C
g
g
C C
g
e
( )
2 2
,
1
GD DB D
out p
C C R +
= e
Cascode stage with MOSFET capacitances shown
(Miller approximation applied)
0 =
EE105 Fall 2007 Lecture 21, Slide 27 Prof. Liu, UC Berkeley
Cascode Stage: I/O Impedances
(

|
|
.
|

\
|
+ +
=
1
2
1
1
1
1
GD
m
m
GS
in
C
g
g
C j
Z
e
( )
2 2
1
||
DB GD
D out
C C j
R Z
+
=
e
0 =